A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS.
Luca BertulessiSaleh KarmanDmytro CherniakAlessandro GarghettiCarlo SamoriAndrea L. LacaitaSalvatore LevantinoPublished in: IEEE J. Solid State Circuits (2019)