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A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power.

Alessio SanticcioliMario MercandelliAndrea L. LacaitaCarlo SamoriSalvatore Levantino
Published in: IEEE J. Solid State Circuits (2019)
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