A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS.
Matteo BassiGiovanni BoiFabio PadovanJonas FritzinStefano Di MartinoDaniel KnauderAndrea BevilacquaPublished in: ESSCIRC (2019)
Keyphrases
- communication systems
- clock gating
- power consumption
- cmos technology
- clock frequency
- low power
- high speed
- power dissipation
- information processing systems
- computer systems
- blind equalization
- silicon on insulator
- dielectric constant
- power reduction
- multiple access
- channel estimation
- communication technologies
- underwater acoustic
- data mining
- low cost
- ultra wideband
- low frequency
- nm technology
- circuit design
- data management
- quality of service
- information systems
- metal oxide semiconductor