Ajith Amerasekera

Publication Activity (10 Years)

Years Active: 1993-2016
Publications (10 Years): 2

Top Topics

Power Consumption

Processing Capabilities

Top Venues

IEEE J. Solid State Circuits

Publications

Hyeon-Min Bae, Ajith Amerasekera
Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links. ISSCC (2016)
Gerrit den Besten, Ajith Amerasekera
Session 10 overview: Advanced wireline techniques and PLLs: Wireline subcommittee. ISSCC (2015)
Leland Chang, Ajith Amerasekera, Takashi Hashimoto
ES2: Data centers to support tomorrow's cloud. ISSCC (2014)
Masood Qazi, Ajith Amerasekera, Anantha P. Chandrakasan
A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-µm CMOS for Nonvolatile Processing in Digital Systems. IEEE J. Solid State Circuits 49 (1) (2014)
Nicola Da Dalt, Ajith Amerasekera
ES3: High-speed communications on 4 wheels: What's in your next car? ISSCC (2013)
Masood Qazi, Ajith Amerasekera, Anantha P. Chandrakasan
A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems. ISSCC (2013)
Ajith Amerasekera, Makoto Nagata
Foreword. VLSIC (2012)
Ajith Amerasekera
Ultra low power electronics in the next decade. ISLPED (2010)
Ajith Amerasekera
The Changing Design Landscape. IEEE Des. Test Comput. 25 (4) (2008)
Mike Harwood, Nirmal Warke, Richard Simpson, Tom Leslie, Ajith Amerasekera, Sean Batty, Derek Colman, Eugenia Carr, Venu Gopinathan, Steve Hubbins, Peter Hunt, Andy Joy, Pulkit Khandelwal, Bob Killips, Thomas Krause, Shaun Lytollis, Andy Pickering, Mark Saxton, David Sebastio, Graeme Swanson, Andre Szczepanek, Terry Ward, Jeff Williams, Richard Williams, Tom Willwerth
A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery. ISSCC (2007)
Ajith Amerasekera
Concurrent Optimization of Technology and Design for Nano CMOS. VLSI Design (2007)
Prasun Raha, Scott Randall, Richard Jennings, Bob Helmick, Ajith Amerasekera, Baher Haroun
A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities. ISQED (2002)
Charvaka Duvvury, Ajith Amerasekera
ESD: a pervasive reliability concern for IC technologies. Proc. IEEE 81 (5) (1993)