A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery.
Mike HarwoodNirmal WarkeRichard SimpsonTom LeslieAjith AmerasekeraSean BattyDerek ColmanEugenia CarrVenu GopinathanSteve HubbinsPeter HuntAndy JoyPulkit KhandelwalBob KillipsThomas KrauseShaun LytollisAndy PickeringMark SaxtonDavid SebastioGraeme SwansonAndre SzczepanekTerry WardJeff WilliamsRichard WilliamsTom WillwerthPublished in: ISSCC (2007)
Keyphrases
- high speed
- analog to digital converter
- metal oxide semiconductor
- power consumption
- low power
- circuit design
- cmos image sensor
- decision feedback
- mixed signal
- cmos technology
- low cost
- contrast enhancement
- single chip
- channel estimation
- vlsi circuits
- sigma delta
- image sensor
- dynamic range
- real time
- power supply
- recovery algorithm
- integrated circuit
- wide dynamic range
- nm technology
- analog vlsi
- multipath
- multi channel