Baher Haroun

Publication Activity (10 Years)

Years Active: 1988-2023
Publications (10 Years): 13

Top Topics

Delay Insensitive

Fully Integrated

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Athanasios Ramkaj, Michael Perrott, Baher Haroun, Boris Murmann
High-Linearity High-Bandwidth (>20GHz) T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design. ISCAS (2023)
Subhashish Mukherjee, Yogesh Darwhekar, Jayawardan Janardhanan, Peeyoosh Mirajkar, Raghavendra Reddy, Harish Ramesh, Bichoy Bahr, Jagdish Chand, Uday Meda, Baher Haroun, Shankar Karantha, Ernest Ting-Ta Yen, Keegan Martin, Daniel Gan, Amin Sijelmassi, Sankaran Aniruddhan
A 0.5-to-400MHz Programmable BAW Oscillator with Fractional Output Divider Achieving 4ppm Frequency Stability over Temperature and <95fs Jitter. ISSCC (2023)
Sachin Kalia, Salvatore Finocchiaro, Tolga Dinc, Bichoy Bahr, Ashwin Raghunathan, Gerd Schuppener, Siraj Akhtar, Tobias Fritz, Baher Haroun, Benjamin Cook, Swaminathan Sankaran
20 GHz Fractional-N Analog PLL With a BAW Resonator Based On-Chip 2.5 GHz Reference. IEEE J. Solid State Circuits 57 (5) (2022)
Tolga Dinc, Sachin Kalia, Siraj Akhtar, Baher Haroun, Benjamin Cook, Swaminathan Sankaran
High-Efficiency Class-E Power Amplifiers for mmWave Radar Sensors: Design and Implementation. IEEE J. Solid State Circuits 57 (5) (2022)
Preet Garcha, Viola Schaffer, Baher Haroun, Srinath Ramaswamy, Jim Wieser, Jeffrey H. Lang, Anantha P. Chandrakasan
A Duty-Cycled Integrated-Fluxgate Magnetometer for Current Sensing. IEEE J. Solid State Circuits 57 (9) (2022)
Preet Garcha, Viola Schaffer, Baher Haroun, Srinath Ramaswamy, Jim Wieser, Jeffrey Lang, Anantha P. Chandrakasan
A 770 kS/s Duty-Cycled Integrated-Fluxgate Magnetometer for Contactless Current Sensing. ISSCC (2021)
Sachin Kalia, Bichoy Bahr, Tolga Dinc, Baher Haroun, Swaminathan Sankaran
An Ultra-Low Close-In Phase Noise Series-Resonance BAW Oscillator in a 130-nm BiCMOS process. A-SSCC (2021)
Danielle Griffith, Ernest Ting-Ta Yen, Kaichien Tsai, Habeeb Ur Rahman Mohammed, Baher Haroun, Ali Kiaei, Ahmad Bahai
3.1 An Integrated BAW Oscillator with <±30ppm Frequency Stability Over Temperature, Package Stress, and Aging Suitable for High-Volume Production. ISSCC (2020)
Baher Haroun
Autonomous Vehicles Sensor Needs. ESSCIRC (2018)
Baher Haroun
Autonomous Vehicles SEnsor Needs. ESSDERC (2018)
Aritra Banerjee, Rahmi Hezar, Lei Ding, Baher Haroun
A 29.5 dBm Class-E Outphasing RF Power Amplifier With Efficiency and Output Power Enhancement Circuits in 45nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2017)
Rahmi Hezar, Lei Ding, Aritra Banerjee, Joonhoi Hur, Baher Haroun
A PWM Based Fully Integrated Digital Transmitter/PA for WLAN and LTE Applications. IEEE J. Solid State Circuits 50 (5) (2015)
Lei Ding, Joonhoi Hur, Aritra Banerjee, Rahmi Hezar, Baher Haroun
A 25 dBm Outphasing Power Amplifier With Cross-Bridge Combiners. IEEE J. Solid State Circuits 50 (5) (2015)
Brian P. Ginsburg, Srinath Ramaswamy, Vijay Rentala, Eunyoung Seok, Swaminathan Sankaran, Baher Haroun
A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS. IEEE J. Solid State Circuits 49 (4) (2014)
Aritra Banerjee, Rahmi Hezar, Lei Ding, Nathan Schemm, Baher Haroun
A 29.5 dBm class-E outphasing RF power amplifier with performance enhancement circuits in 45nm CMOS. ESSCIRC (2014)
Krishnaswamy Nagaraj, Anant S. Kamath, Karthik Subburaj, Biman Chattopadhyay, Gopalkrishna Nayak, Satyasai Evani, Neeraj P. Nayak, Indu Prathapan, Frank Zhang, Baher Haroun
Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2013)
Venkatesh Srinivasan, Victoria Wang, Patrick Satarzadeh, Baher Haroun, Marco Corsi
-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS. ISSCC (2012)
Baher Haroun, Gyu-Hyeong Cho
Session 16 overview: Switching power control techniques: Analog subcommittee. ISSCC (2012)
Vijay Rentala, Venkatesh Srinivasan, Victoria Wang, Srinath Ramaswamy, Baher Haroun, Marco Corsi
Low power ADC's for wireless communications. MWSCAS (2012)
Rahmi Hezar, Lars Risbo, Halil Kiper, Mounir Fares, Baher Haroun, Gangadhar Burra, Gabriel Gomez
A 110dB SNR and 0.5mW current-steering audio DAC implemented in 45nm CMOS. ISSCC (2010)
Yogesh K. Ramadass, Ayman A. Fayed, Baher Haroun, Anantha P. Chandrakasan
completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS. ISSCC (2010)
Jinseok Koh, Gabriel Gomez, Khurram Muhammad, Robert Bogdan Staszewski, Baher Haroun
A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS. EURASIP J. Wirel. Commun. Netw. 2006 (2006)
Prasun Raha, Scott Randall, Richard Jennings, Bob Helmick, Ajith Amerasekera, Baher Haroun
A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities. ISQED (2002)
Jerry (Heng-Chih) Lin, Baher Haroun
An embedded 0.8 V/480 μW 6b/22 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique. IEEE J. Solid State Circuits 37 (12) (2002)
Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman
Floorplanning with Datapath Optimization. ISCAS (1995)
Baher Haroun, Behzad Sajjadi
Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses. FPGA (1995)
Reza Golshan, Baher Haroun
A Novel Reduced Swing CMOS Bus Interface Circuit for High Speed Low Power VLSI Systems. ISCAS (1994)
Baher Haroun, Behzard Sajjadi
Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAs. ICCD (1994)
Baher Haroun, Chao Hua Wu
A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic. ISCAS (1994)
Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman
A Floorplanner driven by Structural & Timing Constraints. ISCAS (1994)
F. Rouatbi, Baher Haroun, Asim J. Al-Khalili
Power estimation tool for sub-micron CMOS VLSI circuits. ICCAD (1992)
Baher Haroun, Elie Torbey
Synthesis of Multiple Bus/Functional Unit Architectures Implementing Neural Networks. ICCD (1992)
Baher Haroun, Mohamed I. Elmasry
Architectural synthesis for DSP silicon compilers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (4) (1989)
Baher Haroun, Mohamed I. Elmasry
Automatic synthesis of a multi-bus architecture for DSP. ICCAD (1988)