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Athanasios Ramkaj
ORCID
Publication Activity (10 Years)
Years Active: 2017-2023
Publications (10 Years): 6
Top Topics
Nm Technology
Max Csp
Metal Oxide Semiconductor
Power Supply
Top Venues
ESSCIRC
VLSI Technology and Circuits
ISSCC
ISCAS
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Publications
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Athanasios Ramkaj
,
Michael Perrott
,
Baher Haroun
,
Boris Murmann
High-Linearity High-Bandwidth (>20GHz) T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design.
ISCAS
(2023)
Pietro Caragiulo
,
Athanasios Ramkaj
,
Amin Arbabian
,
Boris Murmann
4x Delta-Interleaved Switched-Capacitor DAC in 16nm FinFET CMOS.
ESSCIRC
(2022)
Athanasios Ramkaj
,
Adalberto Cantoni
,
Gabriele Manganaro
,
Siddharth Devarajan
,
Michiel Steyaert
,
Filip Tavernier
A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET.
VLSI Technology and Circuits
(2022)
Athanasios Ramkaj
,
Juan Carlos Pena Ramos
,
Yifan Lyu
,
Maarten Strackx
,
Marcel J. M. Pelgrom
,
Michiel Steyaert
,
Marian Verhelst
,
Filip Tavernier
A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS.
ISSCC
(2019)
Athanasios Ramkaj
,
Maarten Strackx
,
Michiel S. J. Steyaert
,
Filip Tavernier
A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS.
IEEE J. Solid State Circuits
53 (7) (2018)
Athanasios Ramkaj
,
Maarten Strackx
,
Michiel Steyaert
,
Filip Tavernier
A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW single-channel SAR ADC in 28nm bulk CMOS.
ESSCIRC
(2017)