A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS.
Athanasios RamkajMaarten StrackxMichiel S. J. SteyaertFilip TavernierPublished in: IEEE J. Solid State Circuits (2018)
Keyphrases
- high speed
- low power
- cmos technology
- synthetic aperture radar
- silicon on insulator
- analog to digital converter
- nm technology
- sar images
- single chip
- power consumption
- information extraction
- metal oxide semiconductor
- automatic target recognition
- focal plane
- image reconstruction
- max csp
- database
- parameter estimation
- image sensor
- heavy tailed
- wide dynamic range
- maximum likelihood