Satyasai Evani

Publication Activity (10 Years)

Years Active: 2011-2013
Publications (10 Years): 0

Top Topics

Evolvable Hardware

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Krishnaswamy Nagaraj, Anant S. Kamath, Karthik Subburaj, Biman Chattopadhyay, Gopalkrishna Nayak, Satyasai Evani, Neeraj P. Nayak, Indu Prathapan, Frank Zhang, Baher Haroun
Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2013)
Biman Chattopadhyay, Anant S. Kamath, Satyasai Evani, Karthik Subburaj
A 2GHz Digital PLL, with temperature lock range of -40°C to 125°C, in 45nm CMOS. CICC (2011)