Krishnaswamy Nagaraj

Publication Activity (10 Years)

Years Active: 1995-2021
Publications (10 Years): 4

Top Topics

Phase Locked Loop

Fault Detection

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Mehmet Ince, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, LeRoy Winemberg, Sule Ozev
Fault-based Built-in Self-test and Evaluation of Phase Locked Loops. ACM Trans. Design Autom. Electr. Syst. 26 (3) (2021)
Mehmet Ince, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, LeRoy Winemberg, Sule Ozev
Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection. ETS (2019)
Joonsung Park, Krishnaswamy Nagaraj, Mikel Ash, Ajay Kumar
SAR ADC in 65nm using novel residue boosting. CICC (2017)
Lorenzo Pedala, Ugur Sonmez, Fabio Sebastiano, Kofi A. A. Makinwa, Krishnaswamy Nagaraj, Joonsung Park
An oxide electrothermal filter in standard CMOS. IEEE SENSORS (2016)
Xiao Pu, Mikel Ash, Krishnaswamy Nagaraj, Joonsung Park, Steve Vu, Paul Kimelman, Sean de la Haye
C. IEEE J. Solid State Circuits 50 (9) (2015)
Xiao Pu, Ajay Kumar, Krishnaswamy Nagaraj
Corrections to "Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference". IEEE Trans. Circuits Syst. II Express Briefs (8) (2014)
Amit Kumar Gupta, Krishnaswamy Nagaraj, T. R. Viswanathan
A 1.1mW, 63.7dB-SNDR, 10MHz-BW hybrid voltage -time domain ADC. MWSCAS (2014)
Krishnaswamy Nagaraj, Anant S. Kamath, Karthik Subburaj, Biman Chattopadhyay, Gopalkrishna Nayak, Satyasai Evani, Neeraj P. Nayak, Indu Prathapan, Frank Zhang, Baher Haroun
Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2013)
Xiao Pu, Ajay Kumar, Krishnaswamy Nagaraj
Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference. IEEE Trans. Circuits Syst. II Express Briefs (6) (2012)
Xiao Pu, Krishnaswamy Nagaraj, Jacob A. Abraham, Axel Thomsen
A Novel fractional-n PLL Based on a Simple Reference Multiplier. J. Circuits Syst. Comput. 21 (6) (2012)
Amit Kumar Gupta, Krishnaswamy Nagaraj, T. R. Viswanathan
A Two-Stage ADC Architecture With VCO-Based Second Stage. IEEE Trans. Circuits Syst. II Express Briefs (11) (2011)
Krishnaswamy Nagaraj
New Associate Editors. IEEE J. Solid State Circuits 42 (7) (2007)
Krishnaswamy Nagaraj
New Associate Editor. IEEE J. Solid State Circuits 42 (5) (2007)
Krishnaswamy Nagaraj
New Associate Editor. IEEE J. Solid State Circuits 42 (4) (2007)
Krishnaswamy Nagaraj
New Associate Editor. IEEE J. Solid State Circuits 42 (6) (2007)
Krishnaswamy Nagaraj
Message from the Outgoing Editor-in-Chief. IEEE J. Solid State Circuits 42 (8) (2007)
Krishnaswamy Nagaraj
New Associate Editor. IEEE J. Solid State Circuits 40 (2) (2005)
Krishnaswamy Nagaraj
New Associate Editor. IEEE J. Solid State Circuits 40 (6) (2005)
Krishnaswamy Nagaraj
New Associate Editor. IEEE J. Solid State Circuits 40 (3) (2005)
Krishnaswamy Nagaraj
Editorial. IEEE J. Solid State Circuits 39 (8) (2004)
Gennady Feygin, Krishnaswamy Nagaraj, Ranjan Chattopadhyay, R. Herrera, I. Papantonopoulos, David A. Martin, P. Wu, Shanthi Pavan
A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation. CICC (2001)
Shanthi Pavan, Yannis P. Tsividis, Krishnaswamy Nagaraj
Widely programmable high-frequency continuous-time filters in digital CMOS technology. IEEE J. Solid State Circuits 35 (4) (2000)
Krishnaswamy Nagaraj, David A. Martin, Mark A. Wolfe, Ranjan Chattopadhyay, Shanthi Pavan, Jason Cancio, T. R. Viswanathan
A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process. IEEE J. Solid State Circuits 35 (12) (2000)
Shanthi Pavan, Yannis P. Tsividis, Krishnaswamy Nagaraj
Modeling of accumulation MOS capacitors for analog design in digital VLSI processes. ISCAS (6) (1999)
Krishnaswamy Nagaraj, H. Scott Fetterman, Joseph Anidjar, Stephen H. Lewis, Robert G. Renninger
A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers. IEEE J. Solid State Circuits 32 (3) (1997)
Sami Kiriaki, T. Lakshmi Viswanathan, Gennady Feygin, Robert Bogdan Staszewski, Richard Pierson, Bill Krenik, Michiel de Wit, Krishnaswamy Nagaraj
A 160-MHz analog equalizer for magnetic disk read Channel. IEEE J. Solid State Circuits 32 (11) (1997)
Khong-Meng Tham, Krishnaswamy Nagaraj
A low supply voltage high PSRR voltage reference in CMOS process. IEEE J. Solid State Circuits 30 (5) (1995)