Gennady Feygin

Publication Activity (10 Years)

Years Active: 1991-2017
Publications (10 Years): 3

Top Topics

Fourier Transform

Image And Video Compression

Error Correction

Zernike Moments

Top Venues

IEEE Trans. Inf. Theory

Publications

Mostafa El-Khamy, Hessam Mahdavifar, Gennady Feygin, Jungwon Lee, Inyup Kang
Relaxed Polar Codes. IEEE Trans. Inf. Theory 63 (4) (2017)
Mostafa El-Khamy, Hessam Mahdavifar, Gennady Feygin, Jungwon Lee, Inyup Kang
Relaxed channel polarization for reduced complexity polar coding. WCNC (2015)
Mostafa El-Khamy, Hessam Mahdavifar, Gennady Feygin, Jungwon Lee, Inyup Kang
Relaxed Polar Codes. CoRR (2015)
Jaimin Mehta, Robert Bogdan Staszewski, Oren E. Eliezer, Sameh Rezeq, Khurram Waheed, Mitch Entezari, Gennady Feygin, Sudheer K. Vemulapalli, Vasile Zoicas, Chih-Ming Hung, Nathen Barton, Imran Bashir, Kenneth Maggio, Michel Frechette, Meng-Chang Lee, John L. Wallberg, Patrick Cruise, Naveen K. Yanduru
all-digital SAW-less polar transmitter in 65nm EDGE SoC. ISSCC (2010)
Robert Bogdan Staszewski, Dirk Leipold, Oren E. Eliezer, Mitch Entezari, Khurram Muhammad, Imran Bashir, Chih-Ming Hung, John L. Wallberg, Roman Staszewski, Patrick Cruise, Sameh Rezeq, Sudheer K. Vemulapalli, Khurram Waheed, Nathen Barton, Meng-Chang Lee, Chan Fernando, Kenneth Maggio, Tom Jung, Imtinan Elahi, S. Larson, Thomas Murphy, Gennady Feygin, Irene Yuanying Deng, Terry Mayhugh Jr., Y.-C. Ho, K.-M. Low, C. Lin, J. Jaehnig, J. Kerr, Jaimin Mehta, S. Glock, T. Almholt, Sumeer Bhatara
Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS. ISSCC (2008)
Robert Bogdan Staszewski, John L. Wallberg, Chih-Ming Hung, Gennady Feygin, Mitch Entezari, Dirk Leipold
LMS-based calibration of an RF digitally controlled oscillator for mobile phones. IEEE Trans. Circuits Syst. II Express Briefs (3) (2006)
Gennady Feygin, Krishnaswamy Nagaraj, Ranjan Chattopadhyay, R. Herrera, I. Papantonopoulos, David A. Martin, P. Wu, Shanthi Pavan
A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation. CICC (2001)
Sami Kiriaki, T. Lakshmi Viswanathan, Gennady Feygin, Robert Bogdan Staszewski, Richard Pierson, Bill Krenik, Michiel de Wit, Krishnaswamy Nagaraj
A 160-MHz analog equalizer for magnetic disk read Channel. IEEE J. Solid State Circuits 32 (11) (1997)
David Yeh, Gennady Feygin, Paul Chow
RACER: a reconfigurable constraint-length 14 Viterbi decoder. FCCM (1996)
Gennady Feygin, P. Glenn Gulak, Paul Chow
Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding. Inf. Process. Manag. 30 (6) (1994)
Gennady Feygin, P. Glenn Gulak, Paul Chow
Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression. Data Compression Conference (1994)
Gennady Feygin, Patrick Glenn Gulak
Architectural tradeoffs for survivor sequence memory management in Viterbi decoders. IEEE Trans. Commun. 41 (3) (1993)
Gennady Feygin, Patrick Glenn Gulak, Paul Chow
A multiprocessor architecture for Viterbi decoders with linear speedup. IEEE Trans. Signal Process. 41 (9) (1993)
Gennady Feygin, P. Glenn Gulak, Paul Chow
Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding. Data Compression Conference (1993)
Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton
A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. ISCAS (1993)
Gennady Feygin, Patrick Glenn Gulak, Paul Chow
Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up. ICASSP (1991)