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A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation.
Gennady Feygin
Krishnaswamy Nagaraj
Ranjan Chattopadhyay
R. Herrera
I. Papantonopoulos
David A. Martin
P. Wu
Shanthi Pavan
Published in:
CICC (2001)
Keyphrases
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analog to digital converter
low voltage
random access memory
high speed
low power
power consumption
low cost
mixed signal
power supply
control algorithm
analog vlsi
image sequences
steady state
single phase
pac man