Steven J. E. Wilton

ORCID

Publication Activity (10 Years)

Years Active: 1993-2024
Publications (10 Years): 35

Top Venues

FPT

FPL

ACM Trans. Reconfigurable Technol. Syst.

FCCM

Publications

Chris Keilbart, Yuhui Gao, Martin Chua, Eric Matthews, Steven J. E. Wilton, Lesley Shannon
Designing an IEEE-Compliant FPU that Supports Configurable Precision for Soft Processors. ACM Trans. Reconfigurable Technol. Syst. 17 (2) (2024)
Chris Keilbart, Yuhui Gao, Martin Chua, Eric Matthews, Steven J. E. Wilton, Lesley Shannon
Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors. FCCM (2023)
Esther Roorda, Steven J. E. Wilton
Online Training from Streaming Data with Concept Drift on FPGAs. ISQED (2023)
Andrew David Gunter, Steven J. E. Wilton
A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems. FCCM (2023)
Esther Roorda, Seyedramin Rasoulinezhad, Philip H. W. Leong, Steven J. E. Wilton
FPGA Architecture Exploration for DNN Acceleration. ACM Trans. Reconfigurable Technol. Syst. 15 (3) (2022)
Zakary Nafziger, Martin Chua, Daniel Holanda Noronha, Steven J. E. Wilton
Boosting Domain-Specific Debug Through Inter-frame Compression. FPT (2022)
Jose P. Pinilla, Steven J. E. Wilton
Positive-Phase Temperature Scaling for Quantum-Assisted Boltzmann Machine Training. SC (2022)
Kahlan Gibson, Esther Roorda, Daniel Holanda Noronha, Steven J. E. Wilton
Adaptive Clock Management of HLS-generated Circuits on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15 (4) (2022)
Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J. E. Wilton, Wayne Luk
In-circuit tuning of deep learning designs. J. Syst. Archit. 118 (2021)
Daniel Holanda Noronha, Zhiqiang Que, Wayne Luk, Steven J. E. Wilton
Flexible Instrumentation for Live On-Chip Debug of Machine Learning Training on FPGAs. FCCM (2021)
Kahlan Gibson, Esther Roorda, Daniel Holanda Noronha, Steven J. E. Wilton
Syncopation: Adaptive Clock Management for High-Level Synthesis Generated Circuits on FPGAs. FPL (2020)
Al-Shahna Jamal, Eli Cahill, Jeffrey Goeders, Steven J. E. Wilton
Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays. ACM Trans. Reconfigurable Technol. Syst. 13 (1) (2020)
Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J. E. Wilton, Wayne Luk
Towards Overlay-based Rapid In-Circuit Tuning of Deep Learning Designs. FPT (2020)
Jose P. Pinilla, Steven J. E. Wilton
Layout-Aware Embedding for Quantum Annealing Processors. ISC (2019)
Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Steven J. E. Wilton, Wayne Luk
Towards In-Circuit Tuning of Deep Learning Designs. ICCAD (2019)
Daniel Holanda Noronha, Ruizhe Zhao, Zhiqiang Que, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton
An Overlay for Rapid FPGA Debug of Machine Learning Applications. FPT (2019)
Daniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton
On-chip FPGA Debug Instrumentation for Machine Learning Applications. FPGA (2019)
Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton
Architecture Exploration for HLS-Oriented FPGA Debug Overlays. FPGA (2018)
Fatemeh Eslami, Steven J. E. Wilton
Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug. ACM Trans. Design Autom. Electr. Syst. 23 (6) (2018)
Daniel Holanda Noronha, Philip Heng Wai Leong, Steven J. E. Wilton
Kibo: An Open-Source Fixed-Point Tool-kit for Training and Inference in FPGA-Based Deep Learning Networks. IPDPS Workshops (2018)
Deming Chen, Andrew Putnam, Steven J. E. Wilton
Introduction to the Special Section on Deep Learning in FPGAs. ACM Trans. Reconfigurable Technol. Syst. 11 (3) (2018)
Daniel H. Noronha, Bahar Salehpour, Steven J. E. Wilton
LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks. CoRR (2018)
Siddhartha, Steven J. E. Wilton, David Boland, Barry Flower, Perry Blackmore, Philip H. W. Leong
Simultaneous Inference and Training Using On-FPGA Weight Perturbation Techniques. FPT (2018)
Daniel Holanda Noronha, Kahlan Gibson, Bahar Salehpour, Steven J. E. Wilton
LeFlow: Automatic Compilation of TensorFlow Machine Learning Applications to FPGAs. FPT (2018)
Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton
An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug. FPL (2018)
Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton
Extending post-silicon coverage measurement using time-multiplexed FPGA overlays. ETS (2018)
Pavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton
Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques. FPL (2017)
Daniel H. Noronha, Jose P. Pinilla, Steven J. E. Wilton
Rapid circuit-specific inlining tuning for FPGA high-level synthesis. ReConFig (2017)
Jeffrey Goeders, Steven J. E. Wilton
Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (1) (2017)
Jose P. Pinilla, Steven J. E. Wilton
Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs. FPT (2016)
Fatemeh Eslami, Steven J. E. Wilton
An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug. SIGARCH Comput. Archit. News 44 (4) (2016)
Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton
Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges. CoRR (2016)
Jeffrey Goeders, Steven J. E. Wilton
Quantifying observability for in-system debug of high-level synthesis circuits. FPL (2016)
Assem A. M. Bsoul, Steven J. E. Wilton, Kuen Hung Tsoi, Wayne Luk
An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Marco D. Santambrogio, Ramachandran Vaidyanathan, Diana Goehringer, Steven J. E. Wilton
RAW Introduction and Committees. IPDPS Workshops (2016)
Jeffrey Goeders, Steven J. E. Wilton
Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs. FPT (2015)
Jeffrey B. Goeders, Steven J. E. Wilton
Allowing Software Developers to Debug HLS Hardware. CoRR (2015)
Fatemeh Eslami, Steven J. E. Wilton
An adaptive virtual overlay for fast trigger insertion for FPGA debug. FPT (2015)
Jeffrey B. Goeders, Steven J. E. Wilton
Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs. FCCM (2015)
Jürgen Becker, Ken Eguro, Diana Göhringer, Wayne Luk, Marco D. Santambrogio, Ramachandran Vaidyanathan, Steven J. E. Wilton
RAW Introduction and Committees. IPDPS Workshops (2015)
Rehan Ahmed, Steven J. E. Wilton, Peter Hallschmid, Richard Klukas
Hierarchical Dynamic Power-Gating in FPGAs. ARC (2015)
Eddie Hung, Steven J. E. Wilton
Incremental Trace-Buffer Insertion for FPGA Debug. IEEE Trans. Very Large Scale Integr. Syst. 22 (4) (2014)
Eddie Hung, Steven J. E. Wilton
Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network. ACM Trans. Design Autom. Electr. Syst. 19 (2) (2014)
Fatemeh Eslami, Steven J. E. Wilton
Incremental distributed trigger insertion for efficient FPGA debug. FPL (2014)
Rehan Ahmed, Assem A. M. Bsoul, Steven J. E. Wilton, Peter Hallschmid, Richard Klukas
High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs. FPL (2014)
Assem A. M. Bsoul, Steven J. E. Wilton
A Configurable Architecture to Limit Inrush Current in Power-Gated Reconfigurable Devices. J. Low Power Electron. 10 (1) (2014)
Jeffrey B. Goeders, Steven J. E. Wilton
Effective FPGA debug for high-level synthesis generated circuits. FPL (2014)
Eddie Hung, Jeffrey B. Goeders, Steven J. E. Wilton
Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry. ARC (2014)
Jeffrey B. Goeders, Steven J. E. Wilton
Power Aware Architecture Exploration for Field Programmable Gate Arrays. J. Low Power Electron. 10 (3) (2014)
Eddie Hung, Steven J. E. Wilton
Scalable Signal Selection for Post-Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. 21 (6) (2013)
Eddie Hung, Al-Shahna Jamal, Steven J. E. Wilton
Maximum flow algorithms for maximum observability during FPGA debug. FPT (2013)
Joydip Das, Steven J. E. Wilton
Towards development of an analytical model relating FPGA architecture parameters to routability. ACM Trans. Reconfigurable Technol. Syst. 6 (2) (2013)
Eddie Hung, Steven J. E. Wilton
Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers. FPGA (2013)
Eddie Hung, Fatemeh Eslami, Steven J. E. Wilton
Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices. FCCM (2013)
Kyle Balston, Mehdi Karimibiuki, Alan J. Hu, André Ivanov, Steven J. E. Wilton
Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs. IEEE Trans. Computers 62 (2) (2013)
Eddie Hung, Bradley R. Quinton, Steven J. E. Wilton
Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics. IEEE Des. Test 30 (4) (2013)
Steven J. E. Wilton, Bradley R. Quinton, Eddie Hung
Rapid RTL-based signal ranking for FPGA prototyping. FPT (2012)
Eddie Hung, Steven J. E. Wilton
Limitations of incremental signal-tracing for FPGA debug. FPL (2012)
Marcel Gort, Flavio M. de Paula, Johnny J. W. Kuan, Tor M. Aamodt, Alan J. Hu, Steven J. E. Wilton, Jin Yang
Formal-Analysis-Based Trace Computation for Post-Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. 20 (11) (2012)
Kyle Balston, Alan J. Hu, Steven J. E. Wilton, Amir Nahir
Emulation in post-silicon validation: It's not just for functionality anymore. HLDVT (2012)
Assem A. M. Bsoul, Steven J. E. Wilton
A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs. FPGA (2012)
Assem A. M. Bsoul, Steven J. E. Wilton
An FPGA with power-gated switch blocks. FPT (2012)
Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton
Optimizing Floating Point Units in Hybrid FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 20 (7) (2012)
Cindy Mark, Scott Y. L. Chin, Lesley Shannon, Steven J. E. Wilton
Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation. ACM Trans. Embed. Comput. Syst. 11 (S2) (2012)
Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov
Multi-objective voltage island floorplanning using sequence pair representation. Sustain. Comput. Informatics Syst. 2 (2) (2012)
Steven J. E. Wilton, Visvesh Sathe
Advances in 3D design and optimization. CICC (2012)
Jeffrey B. Goeders, Steven J. E. Wilton
VersaPower: Power estimation for diverse FPGA architectures. FPT (2012)
Scott Y. L. Chin, Steven J. E. Wilton
Towards scalable FPGA CAD through architecture. FPGA (2011)
Eddie Hung, Steven J. E. Wilton
On evaluating signal selection algorithms for post-silicon debug. ISQED (2011)
Jeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton
Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition. ReConFig (2011)
Joydip Das, Steven J. E. Wilton
An analytical model relating FPGA architecture parameters to routability. FPGA (2011)
Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov, Res Saleh
Sequence pair based voltage island floorplanning. IGCC (2011)
Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton
Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs). IEEE Trans. Very Large Scale Integr. Syst. 19 (12) (2011)
Joydip Das, Steven J. E. Wilton
Accelerated FPGA architecture design: Capabilities and limitations of analytical models. FPT (2011)
Eddie Hung, Steven J. E. Wilton
Speculative Debug Insertion for FPGAs. FPL (2011)
Joydip Das, Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk
An Analytical Model Relating FPGA Architecture to Logic Density and Depth. IEEE Trans. Very Large Scale Integr. Syst. 19 (12) (2011)
Assem A. M. Bsoul, Steven J. E. Wilton
An FPGA architecture supporting dynamically controlled power gating. FPT (2010)
Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab K. Ward
Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (5) (2010)
Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton
The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). FPGA (2010)
Steven J. E. Wilton
Towards Analytical Methods for FPGA Architecture Investigation. ARC (2010)
Johnny J. W. Kuan, Steven J. E. Wilton, Tor M. Aamodt
Accelerating trace computation in post-silicon debug. ISQED (2010)
Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Ward
Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms. SoC (2009)
Alastair M. Smith, George A. Constantinides, Steven J. E. Wilton, Peter Y. K. Cheung
Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design. FPT (2009)
Scott Y. L. Chin, Steven J. E. Wilton
Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms. ACM Trans. Reconfigurable Technol. Syst. 1 (4) (2009)
Alastair M. Smith, Steven J. E. Wilton, Joydip Das
Wirelength modeling for homogeneous and heterogeneous FPGA architectural development. FPGA (2009)
Scott Y. L. Chin, Steven J. E. Wilton
Improving the memory footprint and runtime scalability of FPGA CAD algorithms. FPL (2009)
Bradley R. Quinton, Steven J. E. Wilton
Programmable Logic Core Enhancements for High-Speed On-Chip Interfaces. IEEE Trans. Very Large Scale Integr. Syst. 17 (9) (2009)
Scott Y. L. Chin, Steven J. E. Wilton
An analytical model relating FPGA architecture and place and route runtime. FPL (2009)
Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip Heng Wai Leong
A detailed delay path model for FPGAs. FPT (2009)
Xiongfei Meng, Resve A. Saleh, Steven J. E. Wilton
Charge-borrowing decap: A novel circuit for removal of local supply noise violations. CICC (2009)
Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Kreidieh Ward
Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT. SoCC (2009)
Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
Floating-Point FPGA: Architecture and Modeling. IEEE Trans. Very Large Scale Integr. Syst. 17 (12) (2009)
Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk
Modeling post-techmapping and post-clustering FPGA circuit depth. FPL (2009)
Steven J. E. Wilton, Arif Rahman
Session 14 - Advanced SoCs - techniques and applications. CICC (2008)
Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk
A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications. ACM Trans. Reconfigurable Technol. Syst. 1 (1) (2008)
Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
Rapid estimation of power consumption for hybrid FPGAs. FPL (2008)
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. IEEE Trans. Very Large Scale Integr. Syst. 16 (11) (2008)
Cindy Mark, Ava Shui, Steven J. E. Wilton
A system-level stochastic circuit generator for FPGA architecture evaluation. FPT (2008)
Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton
On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays. Int. J. Reconfigurable Comput. 2008 (2008)
Chi Wai Yu, Julien Lamoureux, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk
The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units. Int. J. Reconfigurable Comput. 2008 (2008)

Steven J. E. Wilton.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Steven J. E. Wilton