A system-level stochastic circuit generator for FPGA architecture evaluation.
Cindy MarkAva ShuiSteven J. E. WiltonPublished in: FPT (2008)
Keyphrases
- high speed
- hardware architecture
- hardware implementation
- real time
- levels of abstraction
- pipelined architecture
- evaluation model
- low cost
- management system
- hardware design
- software implementation
- systolic array
- monte carlo
- higher level
- network architecture
- circuit design
- expert systems
- real time image processing
- fpga implementation
- power reduction
- hardware architectures
- fpga technology
- information retrieval