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Haile Yu
Publication Activity (10 Years)
Years Active: 2008-2012
Publications (10 Years): 0
Top Topics
Novelty Detection
Signature Recognition
Computing Power
Low Power Consumption
Top Venues
HOST
ASP-DAC
IEEE Trans. Very Large Scale Integr. Syst.
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Publications
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Jie Zhang
,
Haile Yu
,
Qiang Xu
HTOutlier: Hardware Trojan detection with side-channel signature outlier identification.
HOST
(2012)
Haile Yu
,
Philip Heng Wai Leong
,
Qiang Xu
An FPGA Chip Identification Generator Using Configurable Ring Oscillators.
IEEE Trans. Very Large Scale Integr. Syst.
20 (12) (2012)
Yubin Zhang
,
Haile Yu
,
Qiang Xu
CODA: A concurrent online delay measurement architecture for critical paths.
ASP-DAC
(2012)
Haile Yu
,
Qiang Xu
,
Philip Heng Wai Leong
On timing yield improvement for FPGA designs using architectural symmetry (abstract only).
FPGA
(2011)
Haile Yu
,
Qiang Xu
,
Philip Heng Wai Leong
On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry.
FPL
(2011)
Haile Yu
,
Philip Heng Wai Leong
,
Qiang Xu
An FPGA chip identification generator using configurable ring oscillator.
FPT
(2010)
Haile Yu
,
Qiang Xu
,
Philip Heng Wai Leong
Fine-grained characterization of process variation in FPGAs.
FPT
(2010)
Eddie Hung
,
Steven J. E. Wilton
,
Haile Yu
,
Thomas C. P. Chau
,
Philip Heng Wai Leong
A detailed delay path model for FPGAs.
FPT
(2009)
Haile Yu
,
Philip Heng Wai Leong
,
Heiko Hinkelmann
,
Leandro Möller
,
Manfred Glesner
,
Peter Zipf
Towards a unique FPGA-based identification circuit using process variations.
FPL
(2009)
Haile Yu
FPGA interconnect sizing using extended logical effort model.
FPL
(2008)
Haile Yu
,
Yuk Hei Chan
,
Philip Heng Wai Leong
FPGA interconnect design using logical effort.
FPL
(2008)
Haile Yu
,
Yuk Hei Chan
,
Philip Heng Wai Leong
FPGA interconnect design using logical effort.
FPGA
(2008)