Thomas C. P. Chau

Publication Activity (10 Years)

Years Active: 2009-2023
Publications (10 Years): 16

Top Topics

Robotic Control

Neural Architecture

Sequential Monte Carlo

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Lichuan Xiang, Lukasz Dudziak, Mohamed S. Abdelfattah, Thomas C. P. Chau, Nicholas D. Lane, Hongkai Wen
Zero-Cost Operation Scoring in Differentiable Architecture Search. AAAI (2023)
Lichuan Xiang, Lukasz Dudziak, Mohamed S. Abdelfattah, Thomas C. P. Chau, Nicholas D. Lane, Hongkai Wen
Zero-Cost Proxies Meet Differentiable Architecture Search. CoRR (2021)
Abhinav Mehrotra, Alberto Gil C. P. Ramos, Sourav Bhattacharya, Lukasz Dudziak, Ravichander Vipperla, Thomas C. P. Chau, Mohamed S. Abdelfattah, Samin Ishtiaq, Nicholas Donald Lane
NAS-Bench-ASR: Reproducible Neural Architecture Search for Speech Recognition. ICLR (2021)
Mohamed S. Abdelfattah, Lukasz Dudziak, Thomas C. P. Chau, Royson Lee, Hyeji Kim, Nicholas D. Lane
Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator. CoRR (2020)
Thomas C. P. Chau, Lukasz Dudziak, Mohamed S. Abdelfattah, Royson Lee, Hyeji Kim, Nicholas D. Lane
BRP-NAS: Prediction-based NAS using GCNs. CoRR (2020)
Lukasz Dudziak, Thomas C. P. Chau, Mohamed S. Abdelfattah, Royson Lee, Hyeji Kim, Nicholas D. Lane
BRP-NAS: Prediction-based NAS using GCNs. NeurIPS (2020)
Mohamed S. Abdelfattah, Lukasz Dudziak, Thomas C. P. Chau, Royson Lee, Hyeji Kim, Nicholas D. Lane
Codesign-NAS: Automatic FPGA/CNN Codesign Using Neural Architecture Search. FPGA (2020)
Mohamed S. Abdelfattah, Lukasz Dudziak, Thomas C. P. Chau, Royson Lee, Hyeji Kim, Nicholas D. Lane
Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator. DAC (2020)
Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Thomas C. P. Chau
Transparent Heterogeneous Cloud Acceleration. ASAP (2019)
Shengjia Shao, Jason Tsai, Michal Mysior, Wayne Luk, Thomas C. P. Chau, Alexander Warren, Ben Jeppesen
Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control. ASAP (2018)
Thomas C. P. Chau, Pavel Burovskiy, Michael J. Flynn, Wayne Luk
Chapter Two - Advances in Dataflow Systems. Adv. Comput. 106 (2017)
Ben P. Jeppesen, Andrew Crosland, Thomas C. P. Chau
An FPGA-based platform for integrated power and motion control. IECON (2016)
Rocco Morello, Federico Baronti, X. Tian, Thomas C. P. Chau, Roberto Di Rienzo, Roberto Roncella, B. P. Jeppesen, W. H. Lin, T. Ikushima, Roberto Saletti
Hardware-in-the-loop simulation of FPGA-based state estimators for electric vehicle batteries. ISIE (2016)
Shengjia Shao, Liucheng Guo, Ce Guo, Thomas C. P. Chau, David B. Thomas, Wayne Luk, Stephen Weston
Recursive pipelined genetic propagation for bilevel optimisation. FPL (2015)
Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu, Oliver Pell
Automating Elimination of Idle Functions by Runtime Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 8 (3) (2015)
Thomas C. P. Chau, Xinyu Niu, Alison Eele, Jan M. Maciejowski, Peter Y. K. Cheung, Wayne Luk
Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems. ACM Trans. Reconfigurable Technol. Syst. 7 (4) (2015)
Maciej Kurek, Tobias Becker, Thomas C. P. Chau, Wayne Luk
Automating Optimization of Reconfigurable Designs. FCCM (2014)
Thomas C. P. Chau, Maciej Kurek, James Stanley Targett, Jake Humphrey, Georgios Skouroupathis, Alison Eele, Jan M. Maciejowski, Benjamin Cope, Kathryn Cobden, Philip Heng Wai Leong, Peter Y. K. Cheung, Wayne Luk
SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications. FCCM (2014)
Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu
Automating Elimination of Idle Functions by Run-Time Reconfiguration. FCCM (2013)
Thomas C. P. Chau, Xinyu Niu, Alison Eele, Wayne Luk, Peter Y. K. Cheung, Jan M. Maciejowski
Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications. ARC (2013)
Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu
Automating resource optimisation in reconfigurable design (abstract only). FPGA (2013)
Thomas C. P. Chau, James Stanley Targett, Marlon Wijeyasinghe, Wayne Luk, Peter Y. K. Cheung, Benjamin Cope, Alison Eele, Jan M. Maciejowski
Accelerating sequential Monte Carlo method for real-time air traffic management. SIGARCH Comput. Archit. News 41 (5) (2013)
Thomas C. P. Chau, Ka-Wai Kwok, Gary C. T. Chow, Kuen Hung Tsoi, Kit-Hang Lee, Zion Tse, Peter Y. K. Cheung, Wayne Luk
Acceleration of real-time Proximity Query for dynamic active constraints. FPT (2013)
Alison Eele, Jan M. Maciejowski, Thomas C. P. Chau, Wayne Luk
Parallelisation of Sequential Monte Carlo for real-time control in air traffic management. CDC (2013)
Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung, Alison Eele, Jan M. Maciejowski
Adaptive Sequential Monte Carlo approach for real-time applications. FPL (2012)
Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung
Roberts: reconfigurable platform for benchmarking real-time systems. SIGARCH Comput. Archit. News 40 (5) (2012)
Steve C. L. Yuen, Yanqing Ai, Brian P. W. Chan, Thomas C. P. Chau, Sam M. H. Ho, Oscar K. L. Lau, Kong-Pang Pun, Philip Heng Wai Leong, Oliver C. S. Choy
Rapid prototyping on a structured ASIC fabric. ASP-DAC (2010)
Thomas C. P. Chau, David W. L. Wu, Yanqing Ai, Brian P. W. Chan, Sam M. H. Ho, Oscar K. L. Lau, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Philip Heng Wai Leong
Design of a single layer programmable Structured ASIC library. DDECS (2010)
Sam M. H. Ho, Steve C. L. Yuen, Hiu Ching Poon, Thomas C. P. Chau, Yanqing Ai, Philip Heng Wai Leong, Oliver C. S. Choy, Kong-Pang Pun
Structured ASIC: Methodology and comparison. FPT (2010)
Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang
A comparison of via-programmable gate array logic cell circuits. FPGA (2009)
Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip Heng Wai Leong
A detailed delay path model for FPGAs. FPT (2009)
Thomas C. P. Chau, S. Man Ho Ho, Philip Heng Wai Leong, Peter Zipf, Manfred Glesner
Generation of Synthetic Floating-Point benchmark circuits. IPDPS (2009)