On timing yield improvement for FPGA designs using architectural symmetry (abstract only).
Haile YuQiang XuPhilip Heng Wai LeongPublished in: FPGA (2011)
Keyphrases
- high level
- low cost
- real time image processing
- real time
- software architecture
- symmetry detection
- asynchronous circuits
- field programmable gate array
- hardware implementation
- high speed
- significant improvement
- case study
- signal processing
- architectural design
- communication protocol
- single chip
- information systems
- data sets