On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry.

Haile Yu Qiang Xu Philip Heng Wai Leong

Published in: FPL (2011)

Keyphrases

real time
low cost
hardware implementation
high speed
field programmable gate array
fpga implementation
signal processing
hardware design
real time image processing
hardware architectures
image processing
high level
single chip
hardware architecture
architectural models
digital signal