A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs.

Assem A. M. Bsoul Steven J. E. Wilton

Published in: FPGA (2012)

Keyphrases

hardware software
real time
management system
hardware implementation
software architecture
power consumption
design methodology
middle layer
reconfigurable hardware
power management
architectural design
design considerations
changing environment
associative memory
computer systems
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