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Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs.

Jose P. PinillaSteven J. E. Wilton
Published in: FPT (2016)
Keyphrases
  • high level synthesis
  • parallel architecture
  • low cost
  • real world
  • pairwise
  • hardware implementation
  • real time
  • information systems
  • bayesian networks
  • search algorithm
  • real time image processing