Jin Yang

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 12

Top Topics

Messages Exchanged

Hardware And Software

Mining Patterns

Top Venues

Publications

Jin Yang, Zhenkun Yang, Jeremy Casas, Sandip Ray
Correct-by-Construction Design of Custom Accelerator Microarchitectures. IEEE Trans. Computers 73 (1) (2024)
Jin Yang, Jeremy Casas, Zhenkun Yang
Invited: A Scalable Formal Approach for Correctness-Assured Hardware Design. DAC (2023)
Yanzhao Wang, Fei Xie, Zhenkun Yang, Jeremy Casas, Pasquale Cocchini, Jin Yang
An Automated Verification Framework for HalideIR-Based Compiler Transformations. DATE (2023)
Jeremy Casas, Zhenkun Yang, Wen Wang, Jin Yang, Adwait Godbole
Towards A Formally Verified Fully Homomorphic Encryption Compute Engine. DAC (2023)
Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
Mining Patterns From Concurrent Execution Traces. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (8) (2022)
Hao Zheng, Md Rubel Ahmed, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
Model Synthesis for Communication Traces of System Designs. ICCD (2021)
Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
A Comparative Study of Specification Mining Methods for SoC Communication Traces. ISVLSI (2021)
David Shia, Jin Yang
A Hertzian contact based model to estimate thermal resistance of thermal interface material for high-performance microprocessors. Microelectron. J. 112 (2021)
Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang
Mining Message Flows from System-on-Chip Execution Traces. ISQED (2021)
Zhenkun Yang, Yuriy Viktorov, Jin Yang, Jiewen Yao, Vincent Zimmer
UEFI Firmware Fuzzing with Simics Virtual Platform. DAC (2020)
Yuting Cao, Parijat Mukherjee, Mahesh Ketkar, Jin Yang, Hao Zheng
Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs. ISQED (2020)
Hao Zheng, Yuting Cao, Sandip Ray, Jin Yang
Protocol-guided analysis of post-silicon traces under limited observability. ISQED (2016)
Sandip Ray, Jin Yang, Abhishek Basak, Swarup Bhunia
Correctness and security at odds: post-silicon validation of modern SoC designs. DAC (2015)
Sava Krstic, Jin Yang, David W. Palmer, Randy B. Osborne, Eran Talmor
Security of SoC firmware load protocols. HOST (2014)
Ranan Fraer, Doron Keren, Zurab Khasidashvili, Alexander Novakovsky, Avi Puder, Eli Singerman, Eran Talmor, Moshe Y. Vardi, Jin Yang
From visual to logical formalisms for SoC validation. MEMOCODE (2014)
Marcel Gort, Flavio M. de Paula, Johnny J. W. Kuan, Tor M. Aamodt, Alan J. Hu, Steven J. E. Wilton, Jin Yang
Formal-Analysis-Based Trace Computation for Post-Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. 20 (11) (2012)
Doron Bustan, Dmitry Korchemny, Erik Seligman, Jin Yang
SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience. IEEE Des. Test Comput. 29 (2) (2012)
Kecheng Hao, Fei Xie, Sandip Ray, Jin Yang
Optimizing equivalence checking for behavioral synthesis. DATE (2010)
Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Yang
Formal Verification for High-Assurance Behavioral Synthesis. ATVA (2009)
Yan Chen, Fei Xie, Jin Yang
Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation. DAC (2008)
Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton, Jin Yang
BackSpace: Formal Analysis for Post-Silicon Debug. FMCAD (2008)
William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, Marek A. Perkowski
Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (9) (2006)
Jin Yang
Verification Challenges and Opportunities in the New Era of Microprocessor Design. ATVA (2006)
Guowu Yang, Jin Yang, Xiaoyu Song, Fei Xie
Maximal Models of Assertion Graph in GSTE. TAMC (2006)
Guowu Yang, Jin Yang, William N. N. Hung, Xiaoyu Song
Implication of assertion graphs in GSTE. ASP-DAC (2005)
Xiushan Feng, Alan J. Hu, Jin Yang
Partitioned model checking from software specifications. ASP-DAC (2005)
Jin Yang, Avi Puder
Tightly integrate dynamic verification with formal verification: a GSTE based approach. ASP-DAC (2005)
Jin Yang, Carl-Johan H. Seger
Compositional Specification and Model Checking in GSTE. CAV (2004)
William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, Marek A. Perkowski
Quantum logic synthesis by symbolic reachability analysis. DAC (2004)
Jin Yang, Carl-Johan H. Seger
Introduction to generalized symbolic trajectory evaluation. IEEE Trans. Very Large Scale Integr. Syst. 11 (3) (2003)
Alan J. Hu, Jeremy Casas, Jin Yang
Reasoning about GSTE Assertion Graphs. CHARME (2003)
Jin Yang, Carl-Johan H. Seger
Generalized Symbolic Trajectory Evaluation - Abstraction in Action. FMCAD (2002)
Jin Yang, Amit Goel
GSTE through a case study. ICCAD (2002)
Jin Yang, Carl-Johan H. Seger
Introduction to Generalized Symbolic Trajectory Evaluation. ICCD (2001)
Jin Yang, Andreas Tiemeyer
Lazy symbolic model checking. DAC (2000)