David Boland

ORCID

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 37

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

CoRR

FPGA

FPT

Imperial College London, UK (PHD)

Education History

Imperial College London, UK

PHD

Publications

Binglei Lou, David Boland, Philip H. W. Leong
fSEAD: a Composable FPGA-based Streaming Ensemble Anomaly Detection Library. CoRR (2024)
Carol Jingyi Li, Richard Rademacher, David Boland, Craig T. Jin, Chad M. Spooner, Philip H. W. Leong
S$^{3}$CA: A Sparse Strip Spectral Correlation Analyzer. IEEE Signal Process. Lett. 31 (2024)
Binglei Lou, Richard Rademacher, David Boland, Philip H. W. Leong
PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs. CoRR (2024)
Kan Shi, Shuoxiang Xu, Yuhan Diao, David Boland, Yungang Bao
ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration. FPGA (2023)
Xiangwei Li, Douglas L. Maskell, Carol Jingyi Li, Philip H. W. Leong, David Boland
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation. ACM Trans. Reconfigurable Technol. Syst. 16 (1) (2023)
Mohammad Reza Jabbarpour, Bahman Javadi, Philip H. W. Leong, Rodrigo N. Calheiros, David Boland, Chris Butler
Performance Analysis of Federated Learning in Orbital Edge Computing. UCC (2023)
Chuliang Guo, Binglei Lou, Xueyuan Liu, David Boland, Philip H. W. Leong, Cheng Zhuo
BOOST: Block Minifloat-Based On-Device CNN Training Accelerator with Transfer Learning. ICCAD (2023)
Binglei Lou, David Boland, Philip H. W. Leong
fSEAD: A Composable FPGA-based Streaming Ensemble Anomaly Detection Library. ACM Trans. Reconfigurable Technol. Syst. 16 (3) (2023)
Mohammad Reza Jabbarpour, Bahman Javadi, Philip H. W. Leong, Rodrigo N. Calheiros, David Boland, Chris Butler
On-Board Federated Learning in Orbital Edge Computing. ICPADS (2023)
Chuliang Guo, Binglei Lou, Xueyuan Liu, David Boland, Philip H. W. Leong
Single-Batch CNN Training using Block Minifloats on FPGAs. FPGA (2023)
Carol Jingyi Li, Xiangwei Li, Binglei Lou, Craig T. Jin, David Boland, Philip H. W. Leong
Fixed-point FPGA Implementation of the FFT Accumulation Method for Real-time Cyclostationary Analysis. ACM Trans. Reconfigurable Technol. Syst. 16 (3) (2023)
Wenjie Zhou, Haoyan Qi, David Boland, Philip H. W. Leong
FPGA Implementation of N-BEATS for Time Series Forecasting Using Block Minifloat Arithmetic. APCCAS (2022)
Seyedramin Rasoulinezhad, Esther Roorda, Steve Wilton, Philip H. W. Leong, David Boland
Rethinking Embedded Blocks for Machine Learning Applications. ACM Trans. Reconfigurable Technol. Syst. 15 (1) (2022)
Sean Fox, SeyedRamin Rasoulinezhad, Julian Faraone, David Boland, Philip H. W. Leong
A Block Minifloat Representation for Training Deep Neural Networks. ICLR (2021)
SeyedRamin Rasoulinezhad, David Boland, Philip H. W. Leong
MLBlocks: FPGA Blocks for Machine Learning Applications. FPGA (2021)
Stephen Tridgell, David Boland, Philip H. W. Leong, Ryan Kastner, Alireza Khodamoradi, Siddhartha
Real-time Automatic Modulation Classification using RFSoC. IPDPS Workshops (2020)
Joseph Prinable, Peter Jones, David Boland, Alistair Lee McEwan, Cindy Thamrin
Derivation of Respiratory Metrics in Health and Asthma. Sensors 20 (24) (2020)
SeyedRamin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong
LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations. CoRR (2020)
SeyedRamin Rasoulinezhad, Sean Fox, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong
MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency. CoRR (2020)
SeyedRamin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong
LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations. FPGA (2020)
Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, Philip H. W. Leong
AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 28 (1) (2020)
Duncan J. M. Moss, David Boland, Philip H. W. Leong
A Two-Speed, Radix-4, Serial-Parallel Multiplier. IEEE Trans. Very Large Scale Integr. Syst. 27 (4) (2019)
Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan J. M. Moss, Peter Zipf, Philip H. W. Leong
Unrolling Ternary Neural Networks. CoRR (2019)
Sean Fox, Julian Faraone, David Boland, Kees A. Vissers, Philip H. W. Leong
Training Deep Neural Networks in Low-Precision with High Accuracy Using FPGAs. FPT (2019)
Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, Philip H. W. Leong
AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. CoRR (2019)
SeyedRamin Rasoulinezhad, Sean Fox, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong
MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency. FPT (2019)
Stephen Tridgell, David Boland, Philip H. W. Leong, Siddhartha
Real-Time Automatic Modulation Classification. FPT (2019)
Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan J. M. Moss, Peter Zipf, Philip H. W. Leong
Unrolling Ternary Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 12 (4) (2019)
Siddhartha, Yee Hui Lee, Duncan J. M. Moss, Julian Faraone, Perry Blackmore, Daniel Salmond, David Boland, Philip H. W. Leong
Long Short-Term Memory for Radio Frequency Spectral Prediction and its Real-Time FPGA Implementation. MILCOM (2018)
Duncan J. M. Moss, David Boland, Peyam Pourbeik, Philip Heng Wai Leong
Real-time FPGA-based Anomaly Detection for Radio Frequency Signals. ISCAS (2018)
Siddhartha, Steven J. E. Wilton, David Boland, Barry Flower, Perry Blackmore, Philip H. W. Leong
Simultaneous Inference and Training Using On-FPGA Weight Perturbation Techniques. FPT (2018)
Sean Fox, David Boland, Philip Heng Wai Leong
FPGA Fastfood - A High Speed Systolic Implementation of a Large Scale Online Kernel Method. FPGA (2018)
Julian Faraone, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Philip H. W. Leong, David Boland
Customizing Low-Precision Deep Neural Networks for FPGAs. FPL (2018)
Simon Joel Schmidt, David Boland
Dynamic bitwidth assignment for efficient dot products. FPL (2017)
Josh Weberruss, Lindsay Kleeman, David Boland, Tom Drummond
FPGA acceleration of multilevel ORB feature extraction for computer vision. FPL (2017)
Qibing Wang, Binhuang Song, Bill Corcoran, David Boland, Leimeng Zhuang, Yiwei Xie, Arthur J. Lowery
FPGA-based layered/enhanced ACO-OFDM transmitter. OFC (2017)
David Boland
Reducing Memory Requirements for High-Performance and Numerically Stable Gaussian Elimination. FPGA (2016)
Kan Shi, David Boland, George A. Constantinides
Imprecise Datapath Design: An Overclocking Approach. ACM Trans. Reconfigurable Technol. Syst. 8 (2) (2015)
Kan Shi, David Boland, Edward A. Stott, Samuel Bayliss, George A. Constantinides
Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. DAC (2014)
Kan Shi, David Boland, George A. Constantinides
Efficient FPGA implementation of digit parallel online arithmetic operators. FPT (2014)
Kan Shi, David Boland, George A. Constantinides
Overclocking datapath for latency-error tradeoff. ISCAS (2013)
David Boland, George A. Constantinides
Revisiting the reduction circuit: A case study for simultaneous architecture and precision optimisation. FPT (2013)
David Boland, George A. Constantinides
A Scalable Precision Analysis Framework. IEEE Trans. Multim. 15 (2) (2013)
Kan Shi, David Boland, George A. Constantinides
Accuracy-Performance Tradeoffs on an FPGA through Overclocking. FCCM (2013)
David Boland, George A. Constantinides
Word-length optimization beyond straight line code. FPGA (2013)
David Boland, George A. Constantinides
A scalable approach for automated precision analysis. FPGA (2012)
Xuan You Tan, David Boland, George A. Constantinides
FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores. ARC (2012)
David Boland, George A. Constantinides
Optimizing memory bandwidth use and performance for matrix-vector multiplication in iterative methods. ACM Trans. Reconfigurable Technol. Syst. 4 (3) (2011)
Christophe Le Lann, David Boland, George A. Constantinides
The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA. ARC (2011)
David Boland, George A. Constantinides
Bounding Variable Values and Round-Off Effects Using Handelman Representations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (11) (2011)
David Boland, George A. Constantinides
Automated Precision Analysis: A Polynomial Algebraic Approach. FCCM (2010)
David Boland, George A. Constantinides
Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods. ARC (2010)
David Boland, George A. Constantinides
An FPGA-based implementation of the MINRES algorithm. FPL (2008)

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Publication Activity (10 Years)

Top Topics

Top Venues

David Boland