Martin Kumm

ORCID

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 45

Top Venues

University of Kassel, Germany (PHD)

Education History

University of Kassel, Germany

PHD

Publications

Andreas Böttcher, Martin Kumm
Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs. CoRR (2024)
Andreas Böttcher, Martin Kumm
Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs. ARITH (2024)
Andreas Böttcher, Martin Kumm
Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs. CoRR (2024)
Nicolai Fiege, Martin Kumm, Peter Zipf
Bit-Level Optimized Constant Multiplication Using Boolean Satisfiability. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (1) (2024)
Martin Kumm, Anastasia Volkova, Silviu-Ioan Filip
Design of Optimal Multiplierless FIR Filters With Minimal Number of Adders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (2) (2023)
Anastasia Volkova, Rémi Garcia, Florent de Dinechin, Martin Kumm
Hardware-Optimal Digital FIR Filters: One ILP to Rule Them all and in Faithfulness Bind Them. ACSSC (2023)
Martin Hardieck, Tobias Habermann, Fabian Wagner, Michael Mecik, Martin Kumm, Peter Zipf
More AddNet: A deeper insight into DNNs using FPGA-optimized multipliers. ISCAS (2023)
Andreas Böttcher, Martin Kumm
Towards Globally Optimal Design of Multipliers for FPGAs. IEEE Trans. Computers 72 (5) (2023)
Tobias Habermann, Jonas Kühle, Martin Kumm, Anastasia Volkova
Hardware-Aware Quantization for Multiplierless Neural Network Controllers. APCCAS (2022)
Rémi Garcia, Anastasia Volkova, Martin Kumm
Truncated Multiple Constant Multiplication with Minimal Number of Full Adders. ISCAS (2022)
Rémi Garcia, Anastasia Volkova, Martin Kumm, Alexandre Goldsztejn, Jonas Kühle
Hardware-Aware Design of Multiplierless Second-Order IIR Filters With Minimum Adders. IEEE Trans. Signal Process. 70 (2022)
Andreas Böttcher, Martin Kumm, Florent de Dinechin
Resource Optimal Squarers for FPGAs. FPL (2022)
Andreas Böttcher, Martin Kumm, Florent de Dinechin
Resource Optimal Truncated Multipliers for FPGAs. ARITH (2021)
Rémi Garcia, Anastasia Volkova, Martin Kumm, Alexandre Goldsztejn, Jonas Kühle
Hardware-aware Design of Multiplierless Second-Order IIR Filters with Minimum Adders. CoRR (2021)
Florent de Dinechin, Silviu-Ioan Filip, Martin Kumm, Anastasia Volkova
Towards Arithmetic-Centered Filter Design. ARITH (2021)
Andreas Böttcher, Keanu Kullmann, Martin Kumm
Heuristics for the Design of Large Multipliers for FPGAs. ARITH (2020)
Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, Philip H. W. Leong
AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 28 (1) (2020)
Lukas Sommer, Lukas Weber, Martin Kumm, Andreas Koch
Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs. FCCM (2020)
Patrick Sittel, John Wickerson, Martin Kumm, Peter Zipf
Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design. ASP-DAC (2020)
Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan J. M. Moss, Peter Zipf, Philip H. W. Leong
Unrolling Ternary Neural Networks. CoRR (2019)
Mario Garrido, Konrad Möller, Martin Kumm
World's Fastest FFT Architectures: Breaking the Barrier of 100 GS/s. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2019)
Florent de Dinechin, Silviu-Ioan Filip, Martin Kumm, Luc Forget
Table-Based versus Shift-And-Add Constant Multipliers for FPGAs. ARITH (2019)
Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers
Efficient Error-Tolerant Quantized Neural Network Accelerators. DFT (2019)
Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, Philip H. W. Leong
AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. CoRR (2019)
Patrick Sittel, Nicolai Fiege, Martin Kumm, Peter Zipf
Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling. ReConFig (2019)
Martin Hardieck, Martin Kumm, Konrad Möller, Peter Zipf
Reconfigurable Convolutional Kernels for Neural Networks on FPGAs. FPGA (2019)
Julian Oppermann, Patrick Sittel, Martin Kumm, Melanie Reuter-Oppermann, Andreas Koch, Oliver Sinnen
Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling. Euro-Par (2019)
Giulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers
Efficient Error-Tolerant Quantized Neural Network Accelerators. CoRR (2019)
Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan J. M. Moss, Peter Zipf, Philip H. W. Leong
Unrolling Ternary Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 12 (4) (2019)
Martin Kumm, Johannes Kappauf
Advanced Compressor Tree Synthesis for FPGAs. IEEE Trans. Computers 67 (8) (2018)
Patrick Sittel, Thomas Schönwälder, Martin Kumm, Peter Zipf
ScaLP: A Light-Weighted (MI)LP-Library. MBMV (2018)
Martin Kumm
Optimal Constant Multiplication Using Integer Linear Programming. IEEE Trans. Circuits Syst. II Express Briefs (5) (2018)
Konrad Möller, Martin Kumm, Mario Garrido, Peter Zipf
Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (3) (2018)
Martin Kumm, Oscar Gustafsson, Florent de Dinechin, Johannes Kappauf, Peter Zipf
Karatsuba with Rectangular Multipliers for FPGAs. ARITH (2018)
Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf, Andreas Koch
ILP-Based Modulo Scheduling and Binding for Register Minimization. FPL (2018)
Martin Kumm, Oscar Gustafsson, Mario Garrido, Peter Zipf
Optimal Single Constant Multiplication Using Ternary Adders. IEEE Trans. Circuits Syst. II Express Briefs (7) (2018)
Martin Hardieck, Martin Kumm, Patrick Sittel, Peter Zipf
Constant Matrix Multiplication with Ternary Adders. ICECS (2018)
Martin Kumm, Martin Hardieck, Peter Zipf
Optimization of Constant Matrix Multiplication with Low Power and High Throughput. IEEE Trans. Computers 66 (12) (2017)
Patrick Sittel, Martin Kumm, Konrad Möller, Martin Hardieck, Peter Zipf
High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits. MBMV (2017)
Konrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf
Reconfigurable Constant Multiplication for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (6) (2017)
Martin Kumm, Johannes Kappauf, Matei Istoan, Peter Zipf
Resource Optimal Design of Large Multipliers for FPGAs. ARITH (2017)
Patrick Sittel, Konrad Möller, Martin Kumm, Peter Zipf, Bogdan Pasca, Mark Jervis
Model-based hardware design based on compatible sets of isomorphic subgraphs. FPT (2017)
Mario Garrido, Petter Kallstrom, Martin Kumm, Oscar Gustafsson
CORDIC II: A New Improved CORDIC Algorithm. IEEE Trans. Circuits Syst. II Express Briefs (2) (2016)
Martin Kumm, Marco Kleinlein, Peter Zipf
Efficient sum of absolute difference computation on FPGAs. FPL (2016)
Martin Kumm, Peter Zipf
Comment on "High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs". Int. J. Reconfigurable Comput. 2016 (2016)
Mathias Faust, Martin Kumm, Chip-Hong Chang, Peter Zipf
Efficient structural adder pipelining in transposed form FIR filters. DSP (2015)
Konrad Möller, Martin Kumm, Charles-Frederic Müller, Peter Zipf
Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits. CoRR (2015)
Martin Kumm, Shahid Abbas, Peter Zipf
An Efficient Softcore Multiplier Architecture for Xilinx FPGAs. ARITH (2015)
Konrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf
Pipelined reconfigurable multiplication with constants on FPGAs. FPL (2014)
Konrad Möller, Martin Kumm, Björn Barschtipan, Peter Zipf
Dynamically Reconfigurable Constant Multiplication on FPGAs. MBMV (2014)
Martin Kumm, Peter Zipf
Efficient High Speed Compression Trees on Xilinx FPGAs. MBMV (2014)
Martin Kumm, Peter Zipf
Pipelined compressor tree optimization using integer linear programming. FPL (2014)
Martin Kumm, Konrad Möller, Peter Zipf
Reconfigurable FIR filter using distributed arithmetic on FPGAs. ISCAS (2013)
Martin Kumm, Diana Fanghänel, Konrad Möller, Peter Zipf, Uwe Meyer-Baese
FIR filter optimization for video processing on FPGAs. EURASIP J. Adv. Signal Process. 2013 (2013)
Martin Kumm, Konrad Möller, Peter Zipf
Dynamically reconfigurable FIR filter architectures with fast reconfiguration. ReCoSoC (2013)
Martin Kumm, Martin Hardieck, Jens Willkomm, Peter Zipf, Uwe Meyer-Baese
Multiple constant multiplication with ternary adders. FPL (2013)
Martin Kumm, Konrad Möller, Peter Zipf
Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs. ISCAS (2013)
Martin Kumm, Katharina Liebisch, Peter Zipf
Reduced complexity single and multiple constant multiplication in floating point precision. FPL (2012)
Martin Kumm, Peter Zipf, Mathias Faust, Chip-Hong Chang
Pipelined adder graph optimization for high speed multiple constant multiplication. ISCAS (2012)
Martin Kumm, Peter Zipf
Hybrid multiple constant multiplication for FPGAs. ICECS (2012)
Michael Kunz, Martin Kumm, Martin Heide, Peter Zipf
Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system. FPL (2012)
Martin Kumm, Peter Zipf
High speed low complexity FPGA-based FIR filters using pipelined adder graphs. FPT (2011)
Martin Kumm, Harald Klingbeil, Peter Zipf
An FPGA-Based Linear All-Digital Phase-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2010)
Martin Kumm, M. Shahab Sanjari
Digital hilbert transformers for FPGA-based phase-locked loops. FPL (2008)
Andre Guntoro, Peter Zipf, Oliver Soffke, Harald Klingbeil, Martin Kumm, Manfred Glesner
Implementation of Realtime and Highspeed Phase Detector on FPGA. ARC (2006)

Martin Kumm.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Martin Kumm