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More AddNet: A deeper insight into DNNs using FPGA-optimized multipliers.
Martin Hardieck
Tobias Habermann
Fabian Wagner
Michael Mecik
Martin Kumm
Peter Zipf
Published in:
ISCAS (2023)
Keyphrases
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hardware implementation
real time image processing
field programmable gate array
high speed
verilog hdl
data acquisition
databases
low cost
pattern recognition
signal processing
database
decision trees
information retrieval
single chip
real world
low power consumption
digital signal
systolic array