Patrick Sittel

Publication Activity (10 Years)

Years Active: 2017-2022
Publications (10 Years): 12

Top Topics

Hardware Design

Matrix Multiplication

Scheduling Problem

Resource Constraints

Top Venues

Publications

Nicolai Fiege, Patrick Sittel, Peter Zipf
Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals. FPL (2022)
Nicolai Fiege, Patrick Sittel, Peter Zipf
Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis. FPL (2022)
Nicolai Fiege, Patrick Sittel, Peter Zipf
Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling. FCCM (2022)
Patrick Sittel, Nicolai Fiege, John Wickerson, Peter Zipf
Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (3) (2022)
Patrick Sittel, John Wickerson, Martin Kumm, Peter Zipf
Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design. ASP-DAC (2020)
Patrick Sittel, Nicolai Fiege, Martin Kumm, Peter Zipf
Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling. ReConFig (2019)
Julian Oppermann, Patrick Sittel, Martin Kumm, Melanie Reuter-Oppermann, Andreas Koch, Oliver Sinnen
Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling. Euro-Par (2019)
Patrick Sittel, Thomas Schönwälder, Martin Kumm, Peter Zipf
ScaLP: A Light-Weighted (MI)LP-Library. MBMV (2018)
Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf, Andreas Koch
ILP-Based Modulo Scheduling and Binding for Register Minimization. FPL (2018)
Martin Hardieck, Martin Kumm, Patrick Sittel, Peter Zipf
Constant Matrix Multiplication with Ternary Adders. ICECS (2018)
Patrick Sittel, Martin Kumm, Konrad Möller, Martin Hardieck, Peter Zipf
High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits. MBMV (2017)
Patrick Sittel, Konrad Möller, Martin Kumm, Peter Zipf, Bogdan Pasca, Mark Jervis
Model-based hardware design based on compatible sets of isomorphic subgraphs. FPT (2017)