Login / Signup
Model-based hardware design based on compatible sets of isomorphic subgraphs.
Patrick Sittel
Konrad Möller
Martin Kumm
Peter Zipf
Bogdan Pasca
Mark Jervis
Published in:
FPT (2017)
Keyphrases
</>
hardware design
hardware implementation
fpga hardware
neural network
image segmentation
field programmable gate array
social networks
computer vision
information systems
image processing
pattern recognition
scheduling problem
graph cuts
hardware software