Julian Oppermann

ORCID

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 24

Top Venues

Darmstadt University of Technology, Germany (PHD)

Education History

Darmstadt University of Technology, Germany

PHD

Publications

Ettore Tiotto, Victor Perez, Whitney Tsang, Lukas Sommer, Julian Oppermann, Victor Lomüller, Mehdi Goli, James Brodman
Experiences Building an MLIR-Based SYCL Compiler. CGO (2024)
Julian Oppermann, Brindusa Mihaela Damian-Kosterhon, Florian Meisel, Tammo Mürmann, Eyck Jentzsch, Andreas Koch
Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language. ASPLOS (3) (2024)
Victor Perez, Victor Lomüller, Lukas Sommer, Julian Oppermann, Romain Biessy, Tadej Ciglaric, Mehdi Goli
On Demand Specialization of SYCL Kernels with Specialization Constant Length Allocations (SCLA). IWOCL (2024)
Christoph Weckert, Leonardo Solis-Vasquez, Julian Oppermann, Andreas Koch, Oliver Sinnen
Altis-SYCL: Migrating Altis Benchmarking Suite from CUDA to SYCL for GPUs and FPGAs. SC Workshops (2023)
Ettore Tiotto, Victor Perez, Whitney Tsang, Lukas Sommer, Julian Oppermann, Victor Lomüller, Mehdi Goli, James Brodman
Experiences Building an MLIR-based SYCL Compiler. CoRR (2023)
Wolfgang Ecker, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grüttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jörg Bormann, Johannes Partzsch, Christian Mayr, Wolfgang Kunz
The Scale4Edge RISC-V Ecosystem. DATE (2022)
Mihaela Damian, Julian Oppermann, Christoph Spang, Andreas Koch
SCAIE-V: an open-source SCAlable interface for ISA extensions for RISC-V processors. DAC (2022)
Hanna Kruppe, Lukas Sommer, Lukas Weber, Julian Oppermann, Cristian Axenie, Andreas Koch
Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs. SAMOS (2021)
Lukas Weber, Lukas Sommer, Julian Oppermann, Alejandro Molina, Kristian Kersting, Andreas Koch
Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs. FPT (2019)
Julian Oppermann, Lukas Sommer, Lukas Weber, Melanie Reuter-Oppermann, Andreas Koch, Oliver Sinnen
SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis. FPT (2019)
Julian Oppermann, Patrick Sittel, Martin Kumm, Melanie Reuter-Oppermann, Andreas Koch, Oliver Sinnen
Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling. Euro-Par (2019)
Julian Oppermann, Melanie Reuter-Oppermann, Lukas Sommer, Andreas Koch, Oliver Sinnen
Exact and Practical Modulo Scheduling for High-Level Synthesis. ACM Trans. Reconfigurable Technol. Syst. 12 (2) (2019)
Robin Kruppe, Julian Oppermann, Lukas Sommer, Andreas Koch
Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language. CGO (2019)
Julian Oppermann, Lukas Sommer, Andreas Koch
SpExSim: assessing kernel suitability for C-based high-level hardware synthesis. J. Supercomput. 75 (8) (2019)
Julian Oppermann, Sebastian Vollbrecht, Melanie Reuter-Oppermann, Oliver Sinnen, Andreas Koch
GeMS: a generator for modulo scheduling problems: work in progress. CASES (2018)
Julian Oppermann, Melanie Reuter-Oppermann, Lukas Sommer, Oliver Sinnen, Andreas Koch
Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level Synthesis. FPL (2018)
Björn Liebig, Julian Oppermann, Oliver Sinnen, Andreas Koch
Improved High-Level Synthesis for Complex CellML Models. ARC (2018)
Tobias Vinçon, Sergej Hardock, Christian Riegger, Julian Oppermann, Andreas Koch, Ilia Petrov
NoFTL-KV: TacklingWrite-Amplification on KV-Stores with Native Storage Management. EDBT (2018)
Patrick Sittel, Martin Kumm, Julian Oppermann, Konrad Möller, Peter Zipf, Andreas Koch
ILP-Based Modulo Scheduling and Binding for Register Minimization. FPL (2018)
Lukas Sommer, Julian Oppermann, Alejandro Molina, Carsten Binnig, Kristian Kersting, Andreas Koch
Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators. ICCD (2018)
Lukas Sommer, Julian Oppermann, Jaco A. Hofmann, Andreas Koch
Synthesis of interleaved multithreaded accelerators from OpenMP loops. ReConFig (2017)
Julian Oppermann, Andreas Koch, Melanie Reuter-Oppermann, Oliver Sinnen
ILP-based modulo scheduling for high-level synthesis. CASES (2016)
Ting Yu, Julian Oppermann, Chris P. Bradley, Oliver Sinnen
Performance optimisation strategies for automatically generated FPGA accelerators for biomedical models. Concurr. Comput. Pract. Exp. 28 (5) (2016)
Julian Oppermann, Andreas Koch
Detecting Kernels Suitable for C-Based High-Level Hardware Synthesis. UIC/ATC/ScalCom/CBDCom/IoP/SmartWorld (2016)
Julian Oppermann, Andreas Koch, Ting Yu, Oliver Sinnen
Domain-specific optimisation for the high-level synthesis of CellML-based simulation accelerators. FPL (2015)
Jens Huthmann, Julian Oppermann, Andreas Koch
Automatic high-level synthesis of multi-threaded hardware accelerators. FPL (2014)
Jens Huthmann, Björn Liebig, Julian Oppermann, Andreas Koch
Hardware/software co-compilation with the Nymble system. ReCoSoC (2013)

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Publication Activity (10 Years)

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Julian Oppermann