Wolfgang Ecker

ORCID

Publication Activity (10 Years)

Years Active: 1992-2024
Publications (10 Years): 75

Top Venues

Publications

Daniela Sanchez Lopera, Robert Kunzelmann, Endri Kaja, Wolfgang Ecker
Fake Timer: An Engine for Accurate Timing Estimation in Register Transfer Level Designs. ISQED (2024)
Saruni Fernando, Robert Kunzelmann, Daniela Sanchez Lopera, Jad Al Halabi, Wolfgang Ecker
Leveraging Large Language Models for the Automated Documentation of Hardware Designs. MECO (2024)
Mounika Vaddeboina, Endri Kaja, Alper Yilmazer, Uttal Ghosh, Wolfgang Ecker
PaGoRi:A Scalable Parallel Golomb-Rice Decoder. DDECS (2024)
Johannes Schreiner, Daniel Gerl, Robert Kunzelmann, Paritosh Kumar Sinha, Wolfgang Ecker
The Argument for Meta-Modeling-Based Approaches to Hardware Generation Languages. CoRR (2024)
Paul Palomero Bernardo, Patrick Schmid, Oliver Bringmann, Mohammed Iftekhar, Babak Sadiye, Wolfgang Mueller, Andreas Koch, Eyck Jentzsch, Axel Sauer, Ingo Feldner, Wolfgang Ecker
A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. DATE (2024)
Endri Kaja, Nicolas Gerlin, Bihan Zhao, Daniela Sanchez Lopera, Jad Al Halabi, Azam Sher Khan, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification Methods. ISQED (2024)
Erika S. Alcorta, Andreas Gerstlauer, Chenhui Deng, Qi Sun, Zhiru Zhang, Ceyu Xu, Lisa Wu Wills, Daniela Sanchez Lopera, Wolfgang Ecker, Siddharth Garg, Jiang Hu
Special Session: Machine Learning for Embedded System Design. CODES+ISSS (2023)
Saranyu Chattopadhyay, Keerthikumara Devarajegowda, Bihan Zhao, Florian Lonsing, Brandon A. D'Agostino, Ioanna Vavelidou, Vijay Deep Bhatt, Sebastian Prebeck, Wolfgang Ecker, Caroline Trippel, Clark W. Barrett, Subhasish Mitra
G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators. DAC (2023)
Daniela Sanchez Lopera, Ishwor Subedi, Wolfgang Ecker
Using Graph Neural Networks for Timing Estimations of RTL Intermediate Representations. MLCAD (2023)
Endri Kaja, Nicolas Gerlin, Robert Kunzelmann, Keerthikumara Devarajegowda, Wolfgang Ecker
Modelling Peripheral Designs using FSM-like Notation for Complete Property Set Generation. MCSoC (2023)
Johannes Kappes, Robert Kunzelmann, Karsten Emrich, Conrad Foik, Daniel Mueller-Gritschneder, Wolfgang Ecker
Effective Processor Model Generation from Instruction Set Simulator to Hardware Design. NorCAS (2023)
Lorenzo Servadei, Jin Hwa Lee, José Antonio Arjona-Medina, Michael Werner, Sepp Hochreiter, Wolfgang Ecker, Robert Wille
Deep Reinforcement Learning for Optimization at Early Design Stages. IEEE Des. Test 40 (1) (2023)
Daniela Sánchez, Lorenzo Servadei, Gamze Naz Kiprit, Robert Wille, Wolfgang Ecker
A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications. ACM Trans. Design Autom. Electr. Syst. 28 (2) (2023)
Gabriel Rutsch, Konrad Maier, Wolfgang Ecker
FPGA-implementation techniques to efficiently test application readiness of mixed-signal products. VLSI-SoC (2023)
Johannes Schreiner, Vasundhara Raje Gontia, Sebastian Prebeck, Wolfgang Ecker
Generator IP-reuse and Automated Infrastructure Generation for Model-based Full-Chip Generation. MBMV (2023)
Nicolas Gerlin, Endri Kaja, Fabian Vargas, Li Lu, Anselm Breitenreiter, Junchao Chen, Markus Ulbricht, Maribel Gomez, Ares Tahiraga, Sebastian Prebeck, Eyck Jentzsch, Milos Krstic, Wolfgang Ecker
Bits, Flips and RISCs. DDECS (2023)
Mounika Vaddeboina, Endri Kaja, Alper Yilmayer, Sebastian Prebeck, Wolfgang Ecker
Parallel Golomb-Rice Decoder with 8-bit Unary Decoding for Weight Compression in TinyML Applications. DSD (2023)
Wolfgang Ecker, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grüttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jörg Bormann, Johannes Partzsch, Christian Mayr, Wolfgang Kunz
The Scale4Edge RISC-V Ecosystem. DATE (2022)
Nicolas Gerlin, Endri Kaja, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection. VLSI-SoC (2022)
Endri Kaja, Nicolas Gerlin, Monideep Bora, Gabriel Rutsch, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation. VLSI-SoC (2022)
Daniela Sanchez Lopera, Wolfgang Ecker
Applying GNNs to Timing Estimation at RTL. ICCAD (2022)
Endri Kaja, Nicolas Gerlin, Luis Rivas, Monideep Bora, Keerthikumara Devarajegowda, Wolfgang Ecker
MetFI: Model-driven Fault Simulation Framework. CoRR (2022)
Gabriel Rutsch, Maximilian Groebner, Anthony Sanders, Konrad Maier, Wolfgang Ecker
A framework that enables systematic analysis of mixed-signal applications on FPGA. RSP (2022)
Daniela Sanchez Lopera, Lorenzo Servadei, Sebastian Siegfried Prebeck, Wolfgang Ecker
Early RTL delay prediction using neural networks. Microprocess. Microsystems 94 (2022)
Sebastian Siegfried Prebeck, Wafic Lawand, Mounika Vaddeboina, Wolfgang Ecker
A Smart HW-Accelerator for Non-uniform Linear Interpolation of ML-Activation Functions. SAMOS (2022)
Sebastian Prebeck, Sathya Ashok, Mounika Vaddeboina, Keerthikumara Devarajegowda, Wolfgang Ecker
A Scalable, Configurable and Programmable Vector Dot-Product Unit for Edge AI. MBMV (2022)
Steven Herbst, Gabriel Rutsch, Wolfgang Ecker, Mark Horowitz
An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (7) (2022)
Endri Kaja, Nicolas Gerlin, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
MetaFS: Model-driven Fault Simulation Framework. DFT (2022)
Rana Elnaggar, Lorenzo Servadei, Shubham Mathur, Robert Wille, Wolfgang Ecker, Krishnendu Chakrabarty
Accurate and Robust Malware Detection: Running XGBoost on Runtime Data From Performance Counters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (7) (2022)
Christian Lück, Daniela Sanchez Lopera, Sven Wenzek, Wolfgang Ecker
Industrial Experience with Open-Source EDA Tools. MLCAD (2022)
Daniela Sanchez Lopera, Lorenzo Servadei, Gamze Naz Kiprit, Souvik Hazra, Robert Wille, Wolfgang Ecker
A Survey of Graph Neural Networks for Electronic Design Automation. MLCAD (2021)
Oliver Bringmann, Wolfgang Ecker, Ingo Feldner, Adrian Frischknecht, Christoph Gerum, Timo Hämäläinen, Muhammad Abdullah Hanif, Michael J. Klaiber, Daniel Mueller-Gritschneder, Paul Palomero Bernardo, Sebastian Siegfried Prebeck, Muhammad Shafique
Automated HW/SW co-design for edge AI: state, challenges and steps ahead. CODES+ISSS (2021)
Endri Kaja, Nicolas Ojeda Leon, Michael Werner, Bogdan-Andrei Tabacaru, Keerthikumara Devarajegowda, Wolfgang Ecker
Extending Verilator to Enable Fault Simulation. MBMV (2021)
Endri Kaja, Nicolas Gerlin, Mounika Vaddeboina, Luis Rivas, Sebastian Siegfried Prebeck, Zhao Han, Keerthikumara Devarajegowda, Wolfgang Ecker
Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models. DFT (2021)
Zhao Han, Shahzaib Qazi, Michael Werner, Keerthikumara Devarajegowda, Wolfgang Ecker
On Self-Verifying DSL Generation for Embedded Systems Automation. MBMV (2021)
Zhao Han, Deyan Wang, Gabriel Rutsch, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera, Keerthikumara Devarajegowda, Wolfgang Ecker
Aspect-Oriented Design Automation with Model Transformation. VLSI-SoC (2021)
Zhao Han, Gabriel Rutsch, Deyan Wang, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera, Keerthikumara Devarajegowda, Wolfgang Ecker
Transformative Hardware Design Following the Model-Driven Architecture Vision. VLSI-SoC (Selected Papers) (2021)
Keerthikumara Devarajegowda, Endri Kaja, Sebastian Siegfried Prebeck, Wolfgang Ecker
ISA Modeling with Trace Notation for Context Free Property Generation. DAC (2021)
Daniela Sanchez Lopera, Lorenzo Servadei, Vishwa Priyanka Kasi, Sebastian Siegfried Prebeck, Wolfgang Ecker
RTL Delay Prediction Using Neural Networks. NorCAS (2021)
Lorenzo Servadei, Jiapeng Zheng, Jose A. Arjona-Medina, Michael Werner, Volkan Esen, Sepp Hochreiter, Wolfgang Ecker, Robert Wille
Cost Optimization at Early Stages of Design Using Deep Reinforcement Learning. MLCAD (2020)
Michael Werner, Igli Zeraliu, Zhao Han, Sebastian Siegfried Prebeck, Lorenzo Servadei, Wolfgang Ecker
Optimized HW/FW Generation from an Abstract Register Interface Model. DSD (2020)
Antti Rautakoura, Matti Käyrä, Timo D. Hämäläinen, Wolfgang Ecker, Esko Pekkarinen, Mikko Teuho
Kamel: IP-XACT compatible intermediate meta-model for IP generation. DSD (2020)
Lorenzo Servadei, Edoardo Mosca, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker, Robert Wille
Cost Estimation for Configurable Model-Driven SoC Designs Using Machine Learning. ACM Great Lakes Symposium on VLSI (2020)
Vijay Deep Bhatt, Wolfgang Ecker, Volkan Esen, Zhao Han, Daniela Sanchez Lopera, Rituj Patel, Lorenzo Servadei, Sahil Singla, Sven Wenzek, Vijaydeep Yadav, Elena Zennaro
SoC Design Automation with ML - It's Time for Research. MLCAD (2020)
Keerthikumara Devarajegowda, Mohammad Rahmani Fadiheh, Eshan Singh, Clark W. Barrett, Subhasish Mitra, Wolfgang Ecker, Dominik Stoffel, Wolfgang Kunz
QED and Property Generation. DATE (2020)
Michael Werner, Lorenzo Servadei, Robert Wille, Wolfgang Ecker
Automatic compiler optimization on embedded software through k-means clustering. MLCAD (2020)
Lorenzo Servadei, Edoardo Mosca, Elena Zennaro, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker, Robert Wille
Accurate Cost Estimation of Memory Systems Utilizing Machine Learning and Solutions from Computer Vision for Design Automation. IEEE Trans. Computers 69 (6) (2020)
Lorenzo Servadei, Elena Zennaro, Tobias Fritz, Keerthikumara Devarajegowda, Wolfgang Ecker, Robert Wille
Using Machine Learning for predicting area and Firmware metrics of hardware designs from abstract specifications. Microprocess. Microsystems 71 (2019)
Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. DATE (2019)
Lorenzo Servadei, Zhao Han, Michael Werner, Wolfgang Ecker, Keerthikumara Devarajegowda
Formal Verification Methodology in an Industrial Setup. DSD (2019)
Keerthikumara Devarajegowda, Wolfgang Ecker, Wolfgang Kunz
How to Keep 4-Eyes Principle in a Design and Property Generation Flow. MBMV (2019)
Michael Werner, Keerthikumara Devarajegowda, Moomen Chaari, Wolfgang Ecker
Increasing Soft Error Resilience by Software Transformation. DAC (2019)
Lorenzo Servadei, Elena Zennaro, Keerthikumara Devarajegowda, Martin Manzinger, Wolfgang Ecker, Robert Wille
Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision. DATE (2019)
Zhao Han, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker
Towards a Python-Based One Language Ecosystem for Embedded Systems Automation. NORCAS (2019)
Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. CoRR (2019)
Wolfgang Ecker, Keerthikumara Devarajegowda, Michael Werner, Zhao Han, Lorenzo Servadei
Embedded Systems' Automation following OMG's Model Driven Architecture Vision. DATE (2019)
Elena Zennaro, Lorenzo Servadei, Keerthikumara Devarajegowda, Wolfgang Ecker
A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications. DSD (2018)
Lorenzo Servadei, Elena Zennaro, Keerthikumara Devarajegowda, Wolfgang Ecker, Robert Wille
Quality Assessment of Generated Hardware Designs Using Statistical Analysis and Machine Learning. CIMA@ICTAI (2018)
Liang Wu, Mohammad Khizer Hussain, Saed Abughannam, Wolfgang Müller, Christoph Scheytt, Wolfgang Ecker
Analog fault simulation automation at schematic level with random sampling techniques. DTIS (2018)
Keerthikumara Devarajegowda, Wolfgang Ecker
Meta-model Based Automation of Properties for Pre-Silicon Verification. VLSI-SoC (2018)
Daniel Mueller-Gritschneder, Keerthikumara Devarajegowda, Martin Dittrich, Wolfgang Ecker, Marc Greim, Ulf Schlichtmann
The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. RSP (2017)
Keerthikumara Devarajegowda, Johannes Schreiner, Rainer Findenig, Wolfgang Ecker
Python based framework for HDSLs with an underlying formal semantics: (Invited paper). ICCAD (2017)
Keerthikumara Devarajegowda, Wolfgang Ecker
On generation of properties from specification. HLDVT (2017)
Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann
Where formal verification can help in functional safety analysis. ICCAD (2016)
Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello
Gate-Level-Accurate Fault-Effect Analysis at Virtual-Prototype Speed. SAFECOMP Workshops (2016)
Alexander W. Rath, Sebastian Simon, Volkan Esen, Wolfgang Ecker
Automatically comparing analog behavior using Earth Mover's Distance. VLSI-SoC (2016)
Johannes Schreiner, Rainer Findenig, Wolfgang Ecker
Design centric modeling of digital hardware. HLDVT (2016)
Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello
Speeding up safety verification by fault abstraction and simulation to transaction level. VLSI-SoC (2016)
Wolfgang Ecker, Johannes Schreiner
Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators. VLSI-SoC (2016)
Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello, Bogdan-Andrei Tabacaru
Transformation of Failure Propagation Models into Fault Trees for Safety Evaluation Purposes. DSN Workshops (2016)
Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello
Efficient Checkpointing-Based Safety-Verification Flow Using Compiled-Code Simulation. DSD (2016)
Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann
Efficient handling of the fault space in functional safety analysis utilizing formal methods. VLSI-SoC (2016)
Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello
Fault-effect analysis on system-level hardware modeling using virtual prototypes. FDL (2016)
Johannes Schreiner, Wolfgang Ecker
Digital Hardware Design Based on Metamodels and Model Transformations. VLSI-SoC (Selected Papers) (2016)
Alexander W. Rath, Sebastian Simon, Volkan Esen, Wolfgang Ecker
Earth Mover's Distance as a Comparison Metric for Analog Behavior. VLSI-SoC (Selected Papers) (2016)
Oliver Bringmann, Wolfgang Ecker, Andreas Gerstlauer, Ajay Goyal, Daniel Mueller-Gritschneder, Prasanth Sasidharan, Simranjit Singh
The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems. DATE (2015)
Moomen Chaari, Wolfgang Ecker, Cristiano Novello, Bogdan-Andrei Tabacaru, Thomas Kruse
A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systems. DAC (2015)
Wolfgang Ecker, Michael Velten, Leily Zafari, Ajay Goyal
The metamodeling approach to system level synthesis. DATE (2014)
Jan-Hendrik Oetjens, Nico Bannow, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Grüttner, Thomas Kruse, Christoph Kuznik, Hoang Minh Le, Mauderer Mauderer, Wolfgang Müller, Daniel Müller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter, Wolfgang Rosenstiel, S. Roth, Ulf Schlichtmann, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. DAC (2014)
Wolfgang Ecker, Michael Velten, Leily Zafari, Ajay Goyal
Metasynthesis for Designing Automotive SoCs. DAC (2014)
Alexander W. Rath, Volkan Esen, Wolfgang Ecker
A transaction-oriented UVM-based library for verification of analog behavior. ASP-DAC (2014)
Alexander W. Rath, Volkan Esen, Wolfgang Ecker
Comparison of analog transactions using statistics. ISSoC (2013)
Juergen Karmann, Wolfgang Ecker
The semantic of the power intent format UPF: Consistent power modeling from system level to implementation. PATMOS (2013)
Rainer Findenig, Thomas Leitner, Wolfgang Ecker
Transaction-Level Modeling and Refinement Using State Charts. EUROCAST (1) (2013)
Wolfgang Müller, Wolfgang Ecker
Testbenches for advanced TLM verification. CODES+ISSS (2012)
Wolfgang Ecker, Volkan Esen, Michael Velten, Tudor Timisescu
SystemC as completing pillar in industrial OVM based verification environments. CODES+ISSS (2012)
Rainer Findenig, Thomas Leitner, Wolfgang Ecker
Single-source hardware modeling of different abstraction levels with State Charts. HLDVT (2012)
Marcio F. da S. Oliveira, Christoph Kuznik, Hoang Minh Le, Daniel Große, Finn Haedicke, Wolfgang Müller, Rolf Drechsler, Wolfgang Ecker, Volkan Esen
The system verification methodology for advanced TLM verification. CODES+ISSS (2012)
Alexander W. Rath, Volkan Esen, Wolfgang Ecker
Analog transaction level modeling. HLDVT (2011)
Wolfgang Ecker, Pierre Bricaud, Rainer Dömer, Yossi Veller, Stefan Heinen, Jürgen Mössinger, Andreas von Schwerin
Panel Session - Who Is Closing the embedded software design gap? DATE (2010)
Wolfgang Ecker, Volkan Esen, Rainer Findenig, Thomas Steininger, Michael Velten
Model reduction techniques for the formal verification of hardware dependent software. HLDVT (2010)
Rainer Findenig, Thomas Leitner, Michael Velten, Wolfgang Ecker
control flow abstraction. HLDVT (2010)
Wolfgang Ecker, Volkan Esen, Robert Schwencker, Thomas Steininger, Michael Velten
TLM+ modeling of embedded HW/SW systems. DATE (2010)
Rainer Findenig, Wolfgang Ecker
State chart refinement validation from approximately timed to cycle callable models. SoC (2010)
Wolfgang Ecker, Stefan Heinen, Michael Velten
Using a dataflow abstracted virtual prototype for HdS-design. ASP-DAC (2009)
Wido Kruijtzer, Pieter van der Wolf, Erwin A. de Kock, Jan Stuyt, Wolfgang Ecker, Albrecht Mayer, Serge Hustin, Christophe Amerijckx, Serge de Paoli, Emmanuel Vaumorin
Industrial IP Integration Flows based on IP-XACT Standards. DATE (2008)
Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull
Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. DATE (2007)
Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten
Requirements and Concepts for Transaction Level Assertion Refinement. IESS (2007)
Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull
Interactive presentation: Implementation of a transaction level assertion framework in SystemC. DATE (2007)
Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Jacob Smit
IP Library For Temporal SystemC Assertions. FDL (2006)

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Publication Activity (10 Years)

Top Topics

Top Venues

Wolfgang Ecker