Sebastian Siegfried Prebeck

Publication Activity (10 Years)

Years Active: 2020-2022
Publications (10 Years): 9

Top Topics

Hardware Design

Linear Interpolation

Multilayer Perceptron

Top Venues

Publications

Daniela Sanchez Lopera, Lorenzo Servadei, Sebastian Siegfried Prebeck, Wolfgang Ecker
Early RTL delay prediction using neural networks. Microprocess. Microsystems 94 (2022)
Sebastian Siegfried Prebeck, Wafic Lawand, Mounika Vaddeboina, Wolfgang Ecker
A Smart HW-Accelerator for Non-uniform Linear Interpolation of ML-Activation Functions. SAMOS (2022)
Oliver Bringmann, Wolfgang Ecker, Ingo Feldner, Adrian Frischknecht, Christoph Gerum, Timo Hämäläinen, Muhammad Abdullah Hanif, Michael J. Klaiber, Daniel Mueller-Gritschneder, Paul Palomero Bernardo, Sebastian Siegfried Prebeck, Muhammad Shafique
Automated HW/SW co-design for edge AI: state, challenges and steps ahead. CODES+ISSS (2021)
Endri Kaja, Nicolas Gerlin, Mounika Vaddeboina, Luis Rivas, Sebastian Siegfried Prebeck, Zhao Han, Keerthikumara Devarajegowda, Wolfgang Ecker
Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models. DFT (2021)
Zhao Han, Deyan Wang, Gabriel Rutsch, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera, Keerthikumara Devarajegowda, Wolfgang Ecker
Aspect-Oriented Design Automation with Model Transformation. VLSI-SoC (2021)
Zhao Han, Gabriel Rutsch, Deyan Wang, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera, Keerthikumara Devarajegowda, Wolfgang Ecker
Transformative Hardware Design Following the Model-Driven Architecture Vision. VLSI-SoC (Selected Papers) (2021)
Keerthikumara Devarajegowda, Endri Kaja, Sebastian Siegfried Prebeck, Wolfgang Ecker
ISA Modeling with Trace Notation for Context Free Property Generation. DAC (2021)
Daniela Sanchez Lopera, Lorenzo Servadei, Vishwa Priyanka Kasi, Sebastian Siegfried Prebeck, Wolfgang Ecker
RTL Delay Prediction Using Neural Networks. NorCAS (2021)
Michael Werner, Igli Zeraliu, Zhao Han, Sebastian Siegfried Prebeck, Lorenzo Servadei, Wolfgang Ecker
Optimized HW/FW Generation from an Abstract Register Interface Model. DSD (2020)