Keerthikumara Devarajegowda

Publication Activity (10 Years)

Years Active: 2017-2023
Publications (10 Years): 31

Top Topics

Formal Verification

Cost Estimation

Hardware Designs

Instruction Set

Top Venues

Publications

Saranyu Chattopadhyay, Keerthikumara Devarajegowda, Bihan Zhao, Florian Lonsing, Brandon A. D'Agostino, Ioanna Vavelidou, Vijay Deep Bhatt, Sebastian Prebeck, Wolfgang Ecker, Caroline Trippel, Clark W. Barrett, Subhasish Mitra
G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators. DAC (2023)
Endri Kaja, Nicolas Gerlin, Robert Kunzelmann, Keerthikumara Devarajegowda, Wolfgang Ecker
Modelling Peripheral Designs using FSM-like Notation for Complete Property Set Generation. MCSoC (2023)
Nicolas Gerlin, Endri Kaja, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection. VLSI-SoC (2022)
Endri Kaja, Nicolas Gerlin, Monideep Bora, Gabriel Rutsch, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation. VLSI-SoC (2022)
Endri Kaja, Nicolas Gerlin, Luis Rivas, Monideep Bora, Keerthikumara Devarajegowda, Wolfgang Ecker
MetFI: Model-driven Fault Simulation Framework. CoRR (2022)
Sebastian Prebeck, Sathya Ashok, Mounika Vaddeboina, Keerthikumara Devarajegowda, Wolfgang Ecker
A Scalable, Configurable and Programmable Vector Dot-Product Unit for Edge AI. MBMV (2022)
Endri Kaja, Nicolas Gerlin, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
MetaFS: Model-driven Fault Simulation Framework. DFT (2022)
Endri Kaja, Nicolas Ojeda Leon, Michael Werner, Bogdan-Andrei Tabacaru, Keerthikumara Devarajegowda, Wolfgang Ecker
Extending Verilator to Enable Fault Simulation. MBMV (2021)
Endri Kaja, Nicolas Gerlin, Mounika Vaddeboina, Luis Rivas, Sebastian Siegfried Prebeck, Zhao Han, Keerthikumara Devarajegowda, Wolfgang Ecker
Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models. DFT (2021)
Zhao Han, Shahzaib Qazi, Michael Werner, Keerthikumara Devarajegowda, Wolfgang Ecker
On Self-Verifying DSL Generation for Embedded Systems Automation. MBMV (2021)
Zhao Han, Deyan Wang, Gabriel Rutsch, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera, Keerthikumara Devarajegowda, Wolfgang Ecker
Aspect-Oriented Design Automation with Model Transformation. VLSI-SoC (2021)
Zhao Han, Gabriel Rutsch, Deyan Wang, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera, Keerthikumara Devarajegowda, Wolfgang Ecker
Transformative Hardware Design Following the Model-Driven Architecture Vision. VLSI-SoC (Selected Papers) (2021)
Keerthikumara Devarajegowda, Endri Kaja, Sebastian Siegfried Prebeck, Wolfgang Ecker
ISA Modeling with Trace Notation for Context Free Property Generation. DAC (2021)
Lorenzo Servadei, Edoardo Mosca, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker, Robert Wille
Cost Estimation for Configurable Model-Driven SoC Designs Using Machine Learning. ACM Great Lakes Symposium on VLSI (2020)
Keerthikumara Devarajegowda, Mohammad Rahmani Fadiheh, Eshan Singh, Clark W. Barrett, Subhasish Mitra, Wolfgang Ecker, Dominik Stoffel, Wolfgang Kunz
QED and Property Generation. DATE (2020)
Lorenzo Servadei, Edoardo Mosca, Elena Zennaro, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker, Robert Wille
Accurate Cost Estimation of Memory Systems Utilizing Machine Learning and Solutions from Computer Vision for Design Automation. IEEE Trans. Computers 69 (6) (2020)
Lorenzo Servadei, Elena Zennaro, Tobias Fritz, Keerthikumara Devarajegowda, Wolfgang Ecker, Robert Wille
Using Machine Learning for predicting area and Firmware metrics of hardware designs from abstract specifications. Microprocess. Microsystems 71 (2019)
Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. DATE (2019)
Lorenzo Servadei, Zhao Han, Michael Werner, Wolfgang Ecker, Keerthikumara Devarajegowda
Formal Verification Methodology in an Industrial Setup. DSD (2019)
Keerthikumara Devarajegowda, Wolfgang Ecker, Wolfgang Kunz
How to Keep 4-Eyes Principle in a Design and Property Generation Flow. MBMV (2019)
Michael Werner, Keerthikumara Devarajegowda, Moomen Chaari, Wolfgang Ecker
Increasing Soft Error Resilience by Software Transformation. DAC (2019)
Lorenzo Servadei, Elena Zennaro, Keerthikumara Devarajegowda, Martin Manzinger, Wolfgang Ecker, Robert Wille
Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision. DATE (2019)
Zhao Han, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker
Towards a Python-Based One Language Ecosystem for Embedded Systems Automation. NORCAS (2019)
Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. CoRR (2019)
Wolfgang Ecker, Keerthikumara Devarajegowda, Michael Werner, Zhao Han, Lorenzo Servadei
Embedded Systems' Automation following OMG's Model Driven Architecture Vision. DATE (2019)
Elena Zennaro, Lorenzo Servadei, Keerthikumara Devarajegowda, Wolfgang Ecker
A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications. DSD (2018)
Lorenzo Servadei, Elena Zennaro, Keerthikumara Devarajegowda, Wolfgang Ecker, Robert Wille
Quality Assessment of Generated Hardware Designs Using Statistical Analysis and Machine Learning. CIMA@ICTAI (2018)
Keerthikumara Devarajegowda, Wolfgang Ecker
Meta-model Based Automation of Properties for Pre-Silicon Verification. VLSI-SoC (2018)
Daniel Mueller-Gritschneder, Keerthikumara Devarajegowda, Martin Dittrich, Wolfgang Ecker, Marc Greim, Ulf Schlichtmann
The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. RSP (2017)
Keerthikumara Devarajegowda, Johannes Schreiner, Rainer Findenig, Wolfgang Ecker
Python based framework for HDSLs with an underlying formal semantics: (Invited paper). ICCAD (2017)
Keerthikumara Devarajegowda, Wolfgang Ecker
On generation of properties from specification. HLDVT (2017)