Login / Signup
Johannes Schreiner
Publication Activity (10 Years)
Years Active: 2016-2024
Publications (10 Years): 6
Top Topics
Generation Process
Hardware Design
Formal Semantics
Metamodel
Top Venues
CoRR
VLSI-SoC
MBMV
HLDVT
</>
Publications
</>
Johannes Schreiner
,
Daniel Gerl
,
Robert Kunzelmann
,
Paritosh Kumar Sinha
,
Wolfgang Ecker
The Argument for Meta-Modeling-Based Approaches to Hardware Generation Languages.
CoRR
(2024)
Johannes Schreiner
,
Vasundhara Raje Gontia
,
Sebastian Prebeck
,
Wolfgang Ecker
Generator IP-reuse and Automated Infrastructure Generation for Model-based Full-Chip Generation.
MBMV
(2023)
Keerthikumara Devarajegowda
,
Johannes Schreiner
,
Rainer Findenig
,
Wolfgang Ecker
Python based framework for HDSLs with an underlying formal semantics: (Invited paper).
ICCAD
(2017)
Johannes Schreiner
,
Rainer Findenig
,
Wolfgang Ecker
Design centric modeling of digital hardware.
HLDVT
(2016)
Wolfgang Ecker
,
Johannes Schreiner
Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators.
VLSI-SoC
(2016)
Johannes Schreiner
,
Wolfgang Ecker
Digital Hardware Design Based on Metamodels and Model Transformations.
VLSI-SoC (Selected Papers)
(2016)