Edward A. Stott

Publication Activity (10 Years)

Years Active: 2008-2018
Publications (10 Years): 6

Top Topics

Travel Distance

Routing Decisions

Fault Detection

Heterogeneous Systems

Top Venues

Publications

James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. ACM Trans. Reconfigurable Technol. Syst. 11 (1) (2018)
James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. IWOCL (2018)
James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
STRIPE: Signal selection for runtime power estimation. FPL (2017)
James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. IEEE Des. Test 34 (6) (2017)
James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). FPGA (2016)
Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. FCCM (2016)
Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk
Delay-Bounded Routing for Shadow Registers. FPGA (2015)
Sheng Yang, Rishad A. Shafik, Geoff V. Merrett, Edward A. Stott, Joshua M. Levine, James J. Davis, Bashir M. Al-Hashimi
Adaptive energy minimization of embedded heterogeneous systems using regression-based learning. PATMOS (2015)
Kan Shi, David Boland, Edward A. Stott, Samuel Bayliss, George A. Constantinides
Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. DAC (2014)
Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung
Dynamic voltage & frequency scaling with online slack measurement. FPGA (2014)
Edward A. Stott, Joshua M. Levine, Peter Y. K. Cheung, Nachiket Kapre
Timing Fault Detection in FPGA-Based Circuits. FCCM (2014)
Edward A. Stott, Zhenyu Guan, Joshua M. Levine, Justin S. J. Wong, Peter Y. K. Cheung
Variation and Reliability in FPGAs. IEEE Des. Test 30 (6) (2013)
Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
SMI: Slack Measurement Insertion for online timing monitoring in FPGAs. FPL (2013)
Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. FCCM (2012)
Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). FPGA (2011)
Edward A. Stott, Peter Y. K. Cheung
Improving FPGA Reliability with Wear-Levelling. FPL (2011)
Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung
Fault tolerance and reliability in field-programmable gate arrays. IET Comput. Digit. Tech. 4 (3) (2010)
Edward A. Stott, Justin S. J. Wong, Peter Y. K. Cheung
Degradation Analysis and Mitigation in FPGAs. FPL (2010)
Edward A. Stott, Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
Degradation in FPGAs: measurement and modelling. FPGA (2010)
N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung
Compensating for variability in FPGAs by re-mapping and re-placement. FPL (2009)
Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung
Fault tolerant methods for reliability in FPGAs. FPL (2008)