N. Pete Sedcole

Publication Activity (10 Years)

Years Active: 2003-2010
Publications (10 Years): 0

Publications

Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung
Fault tolerance and reliability in field-programmable gate arrays. IET Comput. Digit. Tech. 4 (3) (2010)
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
Wave-pipelined intra-chip signaling for on-FPGA communications. Integr. 43 (2) (2010)
Edward A. Stott, Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
Degradation in FPGAs: measurement and modelling. FPGA (2010)
N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung
Compensating for variability in FPGAs by re-mapping and re-placement. FPL (2009)
Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
Self-Measurement of Combinatorial Circuit Delays in FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2 (2) (2009)
Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung
Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing. ISCAS (2009)
Justin S. J. Wong, Peter Y. K. Cheung, N. Pete Sedcole
Combating process variation on FPGAS with a precise at-speed delay measurement method. FPL (2008)
Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk
Implementation of Wave-Pipelined Interconnects in FPGAs. NOCS (2008)
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
Wave-pipelined signaling for on-FPGA communication. FPT (2008)
N. Pete Sedcole, Peter Y. K. Cheung
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. ACM Trans. Reconfigurable Technol. Syst. 1 (2) (2008)
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
High-throughput interconnect wave-pipelining for global communication in FPGAs. FPGA (2008)
N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung
Characterisation of FPGA Clock Variability. ISVLSI (2008)
Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung
Fault tolerant methods for reliability in FPGAs. FPL (2008)
Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk
Global interconnections in FPGAs: modeling and performance analysis. SLIP (2008)
N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung
Measuring and modeling FPGA clock variability. FPGA (2008)
Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
A transition probability based delay measurement method for arbitrary circuits on FPGAs. FPT (2008)
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
Interconnection lengths and delays estimation for communication links in FPGAs. SLIP (2008)
N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung
Modelling and compensating for clock skew variability in FPGAs. FPT (2008)
N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
Run-Time Integration of Reconfigurable Video Processing Systems. IEEE Trans. Very Large Scale Integr. Syst. 15 (9) (2007)
N. Pete Sedcole, Peter Y. K. Cheung
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. FPGA (2007)
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. NOCS (2007)
Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
Self-characterization of Combinatorial Circuit Delays in FPGAs. FPT (2007)
N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
On-Chip Communication in Run-Time Assembled Reconfigurable Systems. ICSAMOS (2006)
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
On-FPGA Communication Architectures and Design Factors. FPL (2006)
N. Pete Sedcole, Peter Y. K. Cheung
Within-die delay variability in 90nm FPGAs and beyond. FPT (2006)
N. Pete Sedcole, Brandon Blodget, Tobias Becker, James Anderson, Patrick Lysaght
Modular Partial Reconfiguration in Virtex FPGAs. FPL (2005)
N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
A Structured Methodology for System-on-an-FPGA Design. FPL (2004)
N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
A Structured System Methodology for FPGA Based System-on-A-Chip Design. FCCM (2004)
N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
A Reconfigurable Platform for Real-Time Embedded Video Image Processing. FPL (2003)