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Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing.
Li Wang
Terrence S. T. Mak
N. Pete Sedcole
Peter Y. K. Cheung
Published in:
ISCAS (2009)
Keyphrases
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power dissipation
buffer size
response time
low power
high speed
power consumption
data flow
digital signal processing
input output
production system
integrated circuit
face detection
higher throughput
cmos technology
low cost
objective function
multistage
fiber optic
linear array
database
silicon dioxide
real time