Kai-Pui Lam

Publication Activity (10 Years)

Years Active: 1991-2013
Publications (10 Years): 0

Top Topics

Dynamic Optimization

Programmable Logic

Top Venues

Publications

Ra'ed Al-Dujaily, Terrence S. T. Mak, Kai-Pui Lam, Fei Xia, Alex Yakovlev, Chi-Sang Poon
Dynamic On-Chip Thermal Optimization for Three-Dimensional Networks-On-Chip. Comput. J. 56 (6) (2013)
Terrence S. T. Mak, Peter Y. K. Cheung, Kai-Pui Lam, Wayne Luk
Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network. IEEE Trans. Ind. Electron. 58 (8) (2011)
Ra'ed Al-Dujaily, Terrence S. T. Mak, Kuan Zhou, Kai-Pui Lam, Yicong Meng, Alexandre Yakovlev, Chi-Sang Poon
On-chip dynamic programming networks using 3D-TSV integration. ICSAMOS (2011)
Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon
Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC. VLSI-SoC (2011)
Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon
Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network. VLSI-SoC (2011)
Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon
A CMOS Current-Mode Dynamic Programming Circuit. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2010)
Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam
A DP-network for optimal dynamic routing in network-on-chip. CODES+ISSS (2009)
Kai-Pui Lam, H. S. Ng
Intra-daily information of range-based volatility for MEM-GARCH. Math. Comput. Simul. 79 (8) (2009)
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. NOCS (2007)
Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon
A Current-Mode Analog Circuit for Reinforcement Learning Problems. ISCAS (2007)
H. S. Ng, Kai-Pui Lam
How Does Sample Size Affect GARCH Models? JCIS (2006)
Terrence S. T. Mak, Kai-Pui Lam
On Computing Maximum Likelihood Phylogeny Using FPGA p. FPL (2004)
Terrence S. T. Mak, Kai-Pui Lam
FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation. FPL (2004)
Terrence S. T. Mak, Kai-Pui Lam
Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA. CSB (2004)
H. S. Ng, Kai-Pui Lam
Analog and digital FPGA implementation of BRIN for optimization problems. IEEE Trans. Neural Networks 14 (5) (2003)
Terrence S. T. Mak, Kai-Pui Lam
High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign. CSB (2003)
Kai-Pui Lam, Sui-Tung Mak
An FPGA-based eigenfilter using fast Hebbian learning. ICASSP (2) (2003)
H. S. Ng, Sui-Tung Mak, Kai-Pui Lam
Field programmable gate arrays and analog implementation of BRIN for optimization problems. ISCAS (5) (2003)
Ki Chan, Boon Toh Low, Wai Lam, Kai-Pui Lam
Extracting Causation Knowledge from Natural Language Texts. PAKDD (2002)
Kai-Pui Lam, Sui-Tung Mak
On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach. FPL (2002)
Sui-Tung Mak, Kai-Pui Lam
Serial-parallel tradeoff analysis of all-pairs shortest path algorithms in reconfigurable computing. FPT (2002)
Kai-Pui Lam
A binary relation inference network Part 2. State-space techniques. Int. J. Syst. Sci. 27 (4) (1996)
Kai-Pui Lam
A continuous-time inference network and its hybrid implementations. Int. J. Syst. Sci. 27 (12) (1996)
Kai-Pui Lam, Crystal J. Su
A binary relation inference network Part 1. General concepts. Int. J. Syst. Sci. 27 (4) (1996)
Crystal J. Su, Kai-Pui Lam
Digital Circuit Implementation of a Continuous-time Inference Network for the Transitive Closure Problem. ISCAS (1993)
Kai-Pui Lam, Crystal J. Su
On a Binary Relation Inference Network. IPPS (1991)