Jeffrey Goeders

Publication Activity (10 Years)

Years Active: 2012-2023
Publications (10 Years): 22

Top Topics

Novice Programmers

Design Space Exploration

Reverse Engineering

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Reilly McKendrick, Keenan Faulkner, Jeffrey Goeders
Assuring Netlist-to-Bitstream Equivalence using Physical Netlist Generation and Structural Comparison. ICFPT (2023)
Hayden Cook, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders
Improving the Reliability of FPGA CRO PUFs. FPL (2023)
Eli Cahill, Brad L. Hutchings, Jeffrey Goeders
Approaches for FPGA Design Assurance. ACM Trans. Reconfigurable Technol. Syst. 15 (3) (2022)
Hayden Cook, Jacob Arscott, Brent George, Tanner Gaskin, Jeffrey Goeders, Brad L. Hutchings
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits. ACM Trans. Reconfigurable Technol. Syst. 15 (4) (2022)
Reilly McKendrick, Corey Simpson, Brent Nelson, Jeffrey Goeders
Leveraging FPGA Primitives to Improve Word Reconstruction during Netlist Reverse Engineering. FPT (2022)
Hayden Cook, Jonathan Thompson, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders
Cloning the Unclonable: Physically Cloning an FPGA Ring-Oscillator PUF. FPT (2022)
Benjamin James, Jeffrey Goeders
Automated Software Compiler Techniques to Provide Fault Tolerance for Real-Time Operating Systems. DATE (2021)
Tanner Gaskin, Hayden Cook, Wesley Stirk, Robert Lucas, Jeffrey Goeders, Brad L. Hutchings
Using Novel Configuration Techniques for Accelerated FPGA Aging. FPL (2020)
Al-Shahna Jamal, Eli Cahill, Jeffrey Goeders, Steven J. E. Wilton
Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays. ACM Trans. Reconfigurable Technol. Syst. 13 (1) (2020)
Matthew B. Ashcraft, Jeffrey Goeders
Synchronizing On-Chip Software and Hardware Traces for HLS-Accelerated Programs. FPT (2019)
Wesley Stirk, Jeffrey Goeders
Implementation and Design Space Exploration of a Turbo Decoder in High-Level Synthesis. ReConFig (2019)
Daniel Holanda Noronha, Ruizhe Zhao, Zhiqiang Que, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton
An Overlay for Rapid FPGA Debug of Machine Learning Applications. FPT (2019)
Daniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton
On-chip FPGA Debug Instrumentation for Machine Learning Applications. FPGA (2019)
Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton
Architecture Exploration for HLS-Oriented FPGA Debug Overlays. FPGA (2018)
Jeffrey Goeders, Tanner Gaskin, Brad L. Hutchings
Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQ. FCCM (2018)
Adam Hastings, Sean Jensen, Jeffrey Goeders, Brad L. Hutchings
Using Physical and Functional Comparisons to Assure 3rd-Party IP for Modern FPGAs. IVSW (2018)
Matthew B. Ashcraft, Jeffrey Goeders
Unified On-Chip Software and Hardware Debug for HLS-Accelerated Programs. FPT (2018)
Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton
An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug. FPL (2018)
Pavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton
Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques. FPL (2017)
Jeffrey Goeders, Steven J. E. Wilton
Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (1) (2017)
Jeffrey Goeders
Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices. FCCM (2017)
Jeffrey Goeders, Steven J. E. Wilton
Quantifying observability for in-system debug of high-level synthesis circuits. FPL (2016)
Jeffrey Goeders, Steven J. E. Wilton
Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs. FPT (2015)
Jason Luu, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr, Sen Wang, Tim Liu, Nooruddin Ahmed, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
VTR 7.0: Next Generation Architecture and CAD System for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 7 (2) (2014)
Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson
The VTR project: architecture and CAD for FPGAs from verilog to routing. FPGA (2012)