Guy G. Lemieux

Publication Activity (10 Years)

Years Active: 1997-2011
Publications (10 Years): 0

Publications

Christopher Han-Yu Chou, Aaron Severance, Alex D. Brant, Zhiduo Liu, Saurabh Sant, Guy G. Lemieux
VEGAS: soft vector processor with scratchpad memory. FPGA (2011)
David Grant, Chris Wang, Guy G. Lemieux
A CAD framework for Malibu: an FPGA with time-multiplexed coarse-grained elements. FPGA (2011)
Chris C. Wang, Guy G. Lemieux
Scalable and deterministic timing-driven parallel placement for FPGAs. FPGA (2011)
Jonathan Rose, Guy G. Lemieux
The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop. FPGA (2011)
Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton
Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs). IEEE Trans. Very Large Scale Integr. Syst. 19 (12) (2011)
Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton
The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). FPGA (2010)
Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet
Estimating reliability and throughput of source-synchronous wave-pipelined interconnect. NOCS (2009)
David Leong, Guy G. Lemieux
Replace: An incremental placement algorithm for field programmable gate arrays. FPL (2009)
Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. FPGA (2009)
Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux
Vector Processing as a Soft Processor Accelerator. ACM Trans. Reconfigurable Technol. Syst. 2 (2) (2009)
Johnny Tsung Lin Ho, Guy G. Lemieux
PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions. FPGA (2009)
David Grant, Guy G. Lemieux
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing. ACM Trans. Reconfigurable Technol. Syst. 1 (3) (2008)
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. IEEE Trans. Very Large Scale Integr. Syst. 16 (11) (2008)
Guy G. Lemieux, Tarek A. El-Ghazawi
Designing with extreme parallelism. FPGA (2008)
Tarek A. El-Ghazawi, Guy G. Lemieux
Extreme parallel architectures for the masses. FPGA (2008)
Jason Yu, Guy G. Lemieux, Christopher Eagleston
Vector processing as a soft-core CPU accelerator. FPGA (2008)
Paul Teehan, Mark R. Greenstreet, Guy G. Lemieux
A Survey and Taxonomy of GALS Design Styles. IEEE Des. Test Comput. 24 (5) (2007)
David Yeager, Darius Chiu, Guy G. Lemieux
Congestion estimation and localization in FPGAS: a visual tool for interconnect prediction. SLIP (2007)
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton
GlitchLess: an active glitch minimization technique for FPGAs. FPGA (2007)
Marvin Tom, David Leong, Guy G. Lemieux
Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. ICCAD (2006)
David Grant, Scott Chin, Guy G. Lemieux
Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools. FPL (2006)
Marvin Tom, Guy G. Lemieux
Logic block clustering of large designs for channel-width constrained FPGAs. DAC (2005)
Anthony J. Yu, Guy G. Lemieux
FPGA Defect Tolerance: Impact of Granularity. FPT (2005)
Anthony J. Yu, Guy G. Lemieux
Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement. FPL (2005)
Guy G. Lemieux, David M. Lewis
Analytical Framework for Switch Block Design. FPL (2002)
Guy G. Lemieux, David M. Lewis
Circuit design of routing switches. FPGA (2002)
Guy G. Lemieux, David M. Lewis
Using sparse crossbars within LUT. FPGA (2001)
R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
The NUMAchine Multiprocessor. ICPP (2000)
Guy G. Lemieux, Paul Leventis, David M. Lewis
Generating highly-routable sparse crossbars for PLDs. FPGA (2000)
A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
Design and Implementation of the NUMAchine Multiprocessor. DAC (1998)
Guy G. Lemieux, Stephen Dean Brown, Daniel Vranesic
On two-step routing for FPGAS. ISPD (1997)