Stephen Dean Brown

Publication Activity (10 Years)

Years Active: 1990-2018
Publications (10 Years): 5

Top Topics

Parallel Hardware

Embedded Systems

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Bain Syrowik, Blair Fort, Stephen Dean Brown
Use of CPU Performance Counters for Accelerator Selection in HLS-Generated CPU-Accelerator Systems. HEART (2018)
Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson
From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 25 (10) (2017)
Kevin Nam, Blair Fort, Stephen Dean Brown
FISH: Linux system calls for FPGA accelerators. FPL (2017)
Jongsok Choi, Ruolong Lian, Stephen Dean Brown, Jason Helge Anderson
A unified software approach to specify pipeline and spatial parallelism in FPGA hardware. ASAP (2016)
Razvan Nane, Vlad Mihai Sima, Christian Pilato, Jongsok Choi, Blair Fort, Andrew Canis, Yu Ting Chen, Hsuan Hsiao, Stephen Dean Brown, Fabrizio Ferrandi, Jason Helge Anderson, Koen Bertels
A Survey and Evaluation of FPGA High-Level Synthesis Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (10) (2016)
Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson
The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware. ACM Trans. Reconfigurable Technol. Syst. 8 (3) (2015)
Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson
Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware. FPT (2015)
Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson
Source-level debugging for FPGA high-level synthesis. FPL (2014)
Andrew Canis, Stephen Dean Brown, Jason Helge Anderson
Modulo SDC scheduling with recurrence minimization in high-level synthesis. FPL (2014)
Blair Fort, Andrew Canis, Jongsok Choi, Nazanin Calagar, Ruolong Lian, Stefan Hadjis, Yu Ting Chen, Mathew Hall, Bain Syrowik, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson
Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis. EUC (2014)
Jiu Cheng Cai, Ruolong Lian, Mengyao Wang, Andrew Canis, Jongsok Choi, Blair Fort, Eric Hart, Emily Miao, Yanyan Zhang, Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson
From C to Blokus Duo with LegUp high-level synthesis. FPT (2013)
Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown
Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs. ACM Trans. Reconfigurable Technol. Syst. 6 (4) (2013)
Andrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang, Nazanin Calagar, Marcel Gort, Jia Jun Qin, Mark Aldham, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson
From software to accelerators with LegUp high-level synthesis. CASES (2013)
Jason Helge Anderson, Stephen Dean Brown, Andrew Canis, Jongsok Choi
High-level synthesis with LegUp: a crash course for users and researchers. FPGA (2013)
Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems. ACM Trans. Embed. Comput. Syst. 13 (2) (2013)
Andrew Canis, Jason Helge Anderson, Stephen Dean Brown
Multi-pumping for resource reduction in FPGA high-level synthesis. DATE (2013)
Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Stephen Dean Brown, Jason Helge Anderson
The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs. FCCM (2013)
Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson
From software threads to parallel hardware in high-level synthesis for FPGAs. FPT (2013)
Stefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Dean Brown, Tomasz S. Czajkowski
Impact of FPGA architecture on resource sharing in high-level synthesis. FPGA (2012)
Jongsok Choi, Kevin Nam, Andrew Canis, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski
Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems. FCCM (2012)
Mark Aldham, Jason Helge Anderson, Stephen Dean Brown, Andrew Canis
Low-cost hardware profiling of run-time and energy in FPGA embedded processors. ASAP (2011)
Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski
LegUp: high-level synthesis for FPGA-based processor/accelerator systems. FPGA (2011)
Andrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu
Toward Automated ECOs in FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (1) (2011)
Tomasz S. Czajkowski, Stephen Dean Brown
Decomposition-Based Vectorless Toggle Rate Computation for FPGA Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (11) (2010)
Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour
Towards automated ECOs in FPGAs. FPGA (2009)
Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown
Enhancements to FPGA design methodology using streaming. FPL (2009)
Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
Scalable Synthesis and Clustering Techniques Using Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (3) (2008)
Tomasz S. Czajkowski, Stephen Dean Brown
Fast toggle rate computation for FPGA circuits. FPL (2008)
Tomasz S. Czajkowski, Stephen Dean Brown
Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (12) (2008)
Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown
Stream Programming for FPGAs. FDL (Selected Papers) (2008)
Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
Delay driven AIG restructuring using slack budget management. ACM Great Lakes Symposium on VLSI (2008)
Tomasz S. Czajkowski, Stephen Dean Brown
Functionally linear decomposition and synthesis of logic circuits for FPGAs. DAC (2008)
Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown
Towards Compilation of Streaming Programs into FPGA Hardware. FDL (2008)
Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown
On Digital Search Trees - A Simple Method for Constructing Balanced Binary Trees. ICSOFT (PL/DPS/KE/MUSE) (2007)
Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (7) (2007)
Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
Incremental placement for structured ASICs using the transportation problem. VLSI-SoC (2007)
Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
BddCut: Towards Scalable Symbolic Cut Enumeration. ASP-DAC (2007)
Deshanand P. Singh, Stephen Dean Brown
An area-efficient timing closure technique for FPGAs using Shannon's expansion. Integr. 40 (2) (2007)
Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. Very Large Scale Integr. Syst. 15 (8) (2007)
Tomasz S. Czajkowski, Stephen Dean Brown
Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits. DAC (2007)
Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
Adaptive FPGAs: High-Level Architecture and a Synthesis Method. FPL (2006)
Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown
A Multithreaded Soft Processor for SoPC Area Reduction. FCCM (2006)
Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD (2006)
Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (11) (2006)
Mehrdad Eslami Dehkordi, Stephen Dean Brown, Terry P. Borer
Modular Partitioning for Incremental Compilation. FPL (2006)
Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP (2006)
Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown
Experiences with Soft-Core Processor Design. IPDPS (2005)
Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
Incremental retiming for FPGA physical synthesis. DAC (2005)
Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
FPGA PLB Evaluation using Quantified Boolean Satisfiability. FPL (2005)
Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
FPGA Logic Synthesis Using Quantified Boolean Satisfiability. SAT (2005)
Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
Two-stage physical synthesis for FPGAs. CICC (2005)
Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown
Post-Placement BDD-Based Decomposition for FPGAs. FPL (2005)
Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
FPGA technology mapping: a study of optimality. DAC (2005)
Shawn Malhotra, Terry P. Borer, Deshanand P. Singh, Stephen Dean Brown
The Quartus University Interface Program: enabling advanced FPGA research. FPT (2004)
Mehrdad Eslami Dehkordi, Stephen Dean Brown
Retiming aware clustering for sequential circuits. FPT (2004)
Deshanand P. Singh, Stephen Dean Brown
An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. VLSI (2003)
Mehrdad Eslami Dehkordi, Stephen Dean Brown
Performance-driven recursive multi-level clustering. FPT (2003)
Deshanand P. Singh, Terry P. Borer, Stephen Dean Brown
Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. VLSI (2003)
Zvonko G. Vranesic, Stephen Dean Brown
Use of HDLs in teaching of computer hardware courses. WCAE (2003)
Mehrdad Eslami Dehkordi, Stephen Dean Brown
Recursive circuit clustering for minimum delay and area. FPGA (2003)
Mehrdad Eslami Dehkordi, Stephen Dean Brown
The effect of cluster packing and node duplication control in delay driven clustering. FPT (2002)
Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. FPL (2002)
Deshanand P. Singh, Stephen Dean Brown
Constrained clock shifting for field programmable gate arrays. FPGA (2002)
Deshanand P. Singh, Stephen Dean Brown
Integrated retiming and placement for field programmable gate arrays. FPGA (2002)
Deshanand P. Singh, Stephen Dean Brown
Incremental placement for layout driven optimizations on FPGAs. ICCAD (2002)
Deshanand P. Singh, Stephen Dean Brown
The case for registered routing switches in field programmable gate arrays. FPGA (2001)
R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
The NUMAchine Multiprocessor. ICPP (2000)
Alireza Kaviani, Stephen Dean Brown
Technology mapping issues for an FPGA with lookup tables and PLA-like blocks. FPGA (2000)
Alireza Kaviani, Stephen Dean Brown
The Hybrid Field-Programmable Architecture. IEEE Des. Test Comput. 16 (2) (1999)
Alireza Kaviani, Daniel Vranesic, Stephen Dean Brown
Computational field programmable architecture. CICC (1998)
Jason Helge Anderson, Stephen Dean Brown
Technology Mapping for Large Complex PLDs. DAC (1998)
Jason Helge Anderson, Stephen Dean Brown
An LPGA with Foldable PLA-style Logic Blocks. FPGA (1998)
A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
Design and Implementation of the NUMAchine Multiprocessor. DAC (1998)
Guy G. Lemieux, Stephen Dean Brown, Daniel Vranesic
On two-step routing for FPGAS. ISPD (1997)
Alireza Kaviani, Stephen Dean Brown
Hybrid FPGA Architecture. FPGA (1996)
Stephen Dean Brown, Jonathan Rose
FPGA and CPLD Architectures: A Tutorial. IEEE Des. Test Comput. 13 (2) (1996)
Stephen Dean Brown
FPGA Architectural Research: A Survey. IEEE Des. Test Comput. 13 (4) (1996)
Stephen Dean Brown, Muhammad M. Khellah, Guy Lemieux
Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays. VLSI Design 4 (4) (1996)
Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic
Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. DAC (1996)
Stephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic
Minimizing FPGA Interconnect Delays. IEEE Des. Test Comput. 13 (4) (1996)
Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
A stochastic model to predict the routability of field-programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (12) (1993)
Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
A detailed router for field-programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (5) (1992)
Benjamin Tseng, Jonathan Rose, Stephen Dean Brown
Improving FPGA Routing Architectures Using Architecture and CAD Interactions. ICCD (1992)
Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
A Detailed Router for Field-Programmable Gate Arrays. ICCAD (1990)