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FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability.
Andrew C. Ling
Deshanand P. Singh
Stephen Dean Brown
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2007)
Keyphrases
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boolean satisfiability
sat solvers
randomly generated
probabilistic planning
genetic algorithm
branch and bound algorithm
hardware implementation
integer linear programming
sat solving
lower bound
decision problems
phase transition
combinatorial problems
symmetry breaking
boolean optimization