Deshanand P. Singh

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 4

Top Topics

Heterogeneous Platforms

Lossless Data Compression

High Level Vision

Top Venues

IEEE Comput. Archit. Lett.

Publications

Rui Ma, Jia-Ching Hsu, Ali Mansoorshahi, Joseph Garvey, Michael Kinsner, Deshanand P. Singh, Derek Chiou
Primate: A Framework to Automatically Generate Soft Processors for Network Applications. IEEE Comput. Archit. Lett. 23 (1) (2024)
Yuan Meng, Michael Kinsner, Deshanand P. Singh, Mahesh A. Iyer, Viktor K. Prasanna
PEARL: Enabling Portable, Productive, and High-Performance Deep Reinforcement Learning using Heterogeneous Platforms. CF (2024)
Ahmed F. AbouElhamayed, Susanne Balle, Deshanand P. Singh, Mohamed S. Abdelfattah
Beyond Inference: Performance Analysis of DNN Server Overheads for Computer Vision. CoRR (2024)
Yuan Meng, Michael Kinsner, Deshanand P. Singh, Mahesh A Iyer, Viktor K. Prasanna
A Software-Hardware Co-Optimized Toolkit for Deep Reinforcement Learning on Heterogeneous Platforms. CoRR (2023)
Deshanand P. Singh, Bogdan Pasca, Tomasz S. Czajkowski
High-Level Design Tools for Floating Point FPGAs. FPGA (2015)
Mohamed S. Abdelfattah, Andrei Hagiescu, Deshanand P. Singh
Gzip on a chip: high performance lossless data compression on FPGAs using OpenCL. IWOCL (2014)
Doris Chen, Deshanand P. Singh
Fractal video compression in OpenCL: An evaluation of CPUs, GPUs, and FPGAs as acceleration platforms. ASP-DAC (2013)
Doris Chen, Deshanand P. Singh
Profile-guided floating- to fixed-point conversion for hybrid FPGA-processor applications. ACM Trans. Archit. Code Optim. 9 (4) (2013)
Deshanand P. Singh, Tomasz S. Czajkowski, Andrew C. Ling
Harnessing the power of FPGAs using altera's OpenCL compiler. FPGA (2013)
Doris Chen, Deshanand P. Singh
Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filtering. FPL (2012)
Tomasz S. Czajkowski, Utku Aydonat, Dmitry Denisenko, John Freeman, Michael Kinsner, David Neto, Jason Wong, Peter Yiannacouras, Deshanand P. Singh
From opencl to high-performance hardware on FPGAS. FPL (2012)
Doris Chen, Deshanand P. Singh
Line-level incremental resynthesis techniques for FPGAs. FPGA (2011)
Doris Chen, Deshanand P. Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs. FPGA (2010)
Doris Chen, Deshanand P. Singh
Parallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs). FPL (2010)
Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (7) (2007)
Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
Incremental placement for structured ASICs using the transportation problem. VLSI-SoC (2007)
Deshanand P. Singh, Stephen Dean Brown
An area-efficient timing closure technique for FPGAs using Shannon's expansion. Integr. 40 (2) (2007)
Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. Very Large Scale Integr. Syst. 15 (8) (2007)
Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD (2006)
Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP (2006)
Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
Incremental retiming for FPGA physical synthesis. DAC (2005)
Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
FPGA PLB Evaluation using Quantified Boolean Satisfiability. FPL (2005)
Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
FPGA Logic Synthesis Using Quantified Boolean Satisfiability. SAT (2005)
Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
Two-stage physical synthesis for FPGAs. CICC (2005)
Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown
Post-Placement BDD-Based Decomposition for FPGAs. FPL (2005)
Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
FPGA technology mapping: a study of optimality. DAC (2005)
Shawn Malhotra, Terry P. Borer, Deshanand P. Singh, Stephen Dean Brown
The Quartus University Interface Program: enabling advanced FPGA research. FPT (2004)
Deshanand P. Singh, Stephen Dean Brown
An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. VLSI (2003)
Deshanand P. Singh, Terry P. Borer, Stephen Dean Brown
Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. VLSI (2003)
Deshanand P. Singh, Stephen Dean Brown
Constrained clock shifting for field programmable gate arrays. FPGA (2002)
Deshanand P. Singh, Stephen Dean Brown
Integrated retiming and placement for field programmable gate arrays. FPGA (2002)
Deshanand P. Singh, Stephen Dean Brown
Incremental placement for layout driven optimizations on FPGAs. ICCAD (2002)
Deshanand P. Singh, Stephen Dean Brown
The case for registered routing switches in field programmable gate arrays. FPGA (2001)