Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow.
Valavan ManohararajahGordon R. ChiuDeshanand P. SinghStephen Dean BrownPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2007)
Keyphrases
- high speed
- power dissipation
- flow patterns
- real time
- computer aided design
- real time image processing
- flow field
- hardware implementation
- field programmable gate array
- computer vision
- low cost
- single chip
- physical world
- texture synthesis
- computer graphics
- case study
- parallel hardware
- solid models
- information flow
- low power
- computer aided
- data acquisition
- design process
- real world