Gordon R. Chiu

Publication Activity (10 Years)

Years Active: 2006-2018
Publications (10 Years): 8

Top Topics

Weakly Supervised

Field Programmable Gate Array

Software Implementation

Top Venues

Publications

Andrew C. Ling, Mohamed S. Abdelfattah, Shane O'Connell, Andrew Bitar, David Han, Roberto DiCecco, Suchit Subhaschandra, Chris N. Johnson, Dmitry Denisenko, Joshua Fender, Gordon R. Chiu
Harnessing Numerical Flexibility for Deep Learning on FPGAs. HEART (2018)
Gordon R. Chiu, Andrew C. Ling, Davor Capalija, Andrew Bitar, Mohamed S. Abdelfattah
Flexibility: FPGAs and CAD in Deep Learning Acceleration. ISPD (2018)
Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu
DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration. CoRR (2018)
Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu
DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration. FPL (2018)
Andrew C. Ling, Utku Aydonat, Shane O'Connell, Davor Capalija, Gordon R. Chiu
Creating High Performance Applications with Intel's FPGA OpenCL™ SDK. IWOCL (2017)
Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu
An OpenCL™ Deep Learning Accelerator on Arria 10. FPGA (2017)
Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu
An OpenCL(TM) Deep Learning Accelerator on Arria 10. CoRR (2017)
David M. Lewis, Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken
The Stratix™ 10 Highly Pipelined FPGA Architecture. FPGA (2016)
Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. Very Large Scale Integr. Syst. 15 (8) (2007)
Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD (2006)
Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP (2006)