Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow.
Valavan ManohararajahGordon R. ChiuDeshanand P. SinghStephen Dean BrownPublished in: SLIP (2006)
Keyphrases
- high speed
- power dissipation
- computer aided design
- computer aided
- hardware implementation
- low cost
- flow patterns
- field programmable gate array
- real time image processing
- data driven
- signal processing
- real time
- object oriented
- clock frequency
- low power
- hardware design
- power reduction
- power consumption
- data acquisition
- neural network
- data flow
- hardware architecture
- cad systems
- design process
- image processing