Valavan Manohararajah

Publication Activity (10 Years)

Years Active: 1997-2016
Publications (10 Years): 1

Top Topics

Fpga Implementation

Top Venues

Publications

David M. Lewis, Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken
The Stratix™ 10 Highly Pipelined FPGA Architecture. FPGA (2016)
Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. Very Large Scale Integr. Syst. 15 (8) (2007)
Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
Adaptive FPGAs: High-Level Architecture and a Synthesis Method. FPL (2006)
Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD (2006)
Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (11) (2006)
Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP (2006)
Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
Incremental retiming for FPGA physical synthesis. DAC (2005)
Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
Two-stage physical synthesis for FPGAs. CICC (2005)
Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown
Post-Placement BDD-Based Decomposition for FPGAs. FPL (2005)
Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. FPL (2002)
Valavan Manohararajah
Rajah: The Design of a Chess Program. J. Int. Comput. Games Assoc. 20 (2) (1997)