Zvonko G. Vranesic

Publication Activity (10 Years)

Years Active: 1970-2013
Publications (10 Years): 0

Top Topics

Multi Dimensional

General Purpose

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown
Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs. ACM Trans. Reconfigurable Technol. Syst. 6 (4) (2013)
Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown
Enhancements to FPGA design methodology using streaming. FPL (2009)
Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown
Stream Programming for FPGAs. FDL (Selected Papers) (2008)
Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown
Towards Compilation of Streaming Programs into FPGA Hardware. FDL (2008)
Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown
On Digital Search Trees - A Simple Method for Constructing Balanced Binary Trees. ICSOFT (PL/DPS/KE/MUSE) (2007)
Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
Adaptive FPGAs: High-Level Architecture and a Synthesis Method. FPL (2006)
Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown
A Multithreaded Soft Processor for SoPC Area Reduction. FCCM (2006)
Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (11) (2006)
Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown
Experiences with Soft-Core Processor Design. IPDPS (2005)
Zvonko G. Vranesic, Stephen Dean Brown
Use of HDLs in teaching of computer hardware courses. WCAE (2003)
Debatosh Debnath, Zvonko G. Vranesic
A fast algorithm for OR-AND-OR synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (9) (2003)
Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. FPL (2002)
Zeljko Zilic, Zvonko G. Vranesic
A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields. IEEE Trans. Computers 51 (9) (2002)
Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
Structural analysis and generation of synthetic digital circuits with memory. IEEE Trans. Very Large Scale Integr. Syst. 9 (1) (2001)
R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
The NUMAchine Multiprocessor. ICPP (2000)
Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
The memory/logic interface in FPGAs with large embedded memory arrays. IEEE Trans. Very Large Scale Integr. Syst. 7 (1) (1999)
Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning. Int. J. Parallel Program. 27 (5) (1999)
Zvonko G. Vranesic
The FPGA Challenge. ISMVL (1998)
Zeljko Zilic, Zvonko G. Vranesic
Using Decision Diagrams to Design ULMs for FPGAs. IEEE Trans. Computers 47 (9) (1998)
A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
Design and Implementation of the NUMAchine Multiprocessor. DAC (1998)
Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
The Multicluster Architecture: Reducing Cycle Time Through Partitioning. MICRO (1997)
Sinisa Srbljic, Zvonko G. Vranesic, Michael Stumm, Leo Budin
Analytical Prediction of Performance for Cache Coherence Protocols. IEEE Trans. Computers 46 (11) (1997)
Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. FPGA (1997)
Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
Memory-System Design Considerations for Dynamically-Scheduled Processors. ISCA (1997)
Zeljko Zilic, Zvonko G. Vranesic
Using BDDs to Design ULMs for FPGAs. FPGA (1996)
Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic
Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. DAC (1996)
Stephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic
Minimizing FPGA Interconnect Delays. IEEE Des. Test Comput. 13 (4) (1996)
Zeljko Zilic, Zvonko G. Vranesic
New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. ISMVL (1996)
Zeljko Zilic, Zvonko G. Vranesic
Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. ISMVL (1995)
Muhammad Jaseemuddin, Zvonko G. Vranesic
Bidirectional Ring: An Alternative to the Hierarchy of Unidirectional Rings. Euro-Par (1995)
Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
Architecture of Centralized Field-Configurable Memory. FPGA (1995)
Keith I. Farkas, Zvonko G. Vranesic, Michael Stumm
Scalable cache consistency for hierarchically structured multiprocessors. J. Supercomput. 8 (4) (1995)
Zeljko Zilic, Zvonko G. Vranesic
A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions. IEEE Trans. Computers 44 (8) (1995)
Sinisa Srbljic, Zvonko G. Vranesic, Leo Budin
Performance Prediction for Different Consistency Schemes in Distributed Shared Memory Systems. HPDC (1994)
Alireza Kaviani, Zvonko G. Vranesic
On Scheduling in Multiprocessor Systems Using Fuzzy Logic. ISMVL (1994)
Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
A stochastic model to predict the routability of field-programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (12) (1993)
Steven J. E. Wilton, Zvonko G. Vranesic
Architectural Support for Block Transfers in a Shared-Memory Multiprocessor. SPDP (1993)
Michiel van de Panne, Eugene Fiume, Zvonko G. Vranesic
Physically Based Modeling and Control of Turning. CVGIP Graph. Model. Image Process. 55 (6) (1993)
Zeljko Zilic, Zvonko G. Vranesic
Current-Mode CMOS Galois Field Circuits. ISMVL (1993)
Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
A detailed router for field-programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (5) (1992)
Keith I. Farkas, Zvonko G. Vranesic, Michael Stumm
Cache Consistency in Hierarchical-Ring-Based Multiprocessors. SC (1992)
Konrad Lei, Zvonko G. Vranesic
Towards the Realization of 4-Valued CMOS Circuits. ISMVL (1992)
Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic
Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs. DAC (1991)
Mostafa I. H. Abd-El-Barr, Zvonko G. Vranesic, Safwat G. Zaky
Algorithmic Synthesis of MVL Functions for CCD Implementation. IEEE Trans. Computers 40 (8) (1991)
Zvonko G. Vranesic, V. Carl Hamacher, A. K. Sanwalka, Safwat G. Zaky
A Hybrid Token/Insertion Ring LAN. INFOCOM (1991)
Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic
Technology Mapping on Lookup Table-Based FPGAs for Performance. ICCAD (1991)
Zvonko G. Vranesic, Michael Stumm, David M. Lewis, Ron White
Hector: A Hierarchically Structured Shared-memory Multiprocessor. Computer 24 (1) (1991)
Konrad Lei, Zvonko G. Vranesic
On the Synthesis of 4-Valued Current Mode CMOS Circuits. ISMVL (1991)
Safwat G. Zaky, Zvonko G. Vranesic, Mostafa I. H. Abd-El-Barr
Step-Wise Synthesis of CCD MVL Functions. ISMVL (1990)
Michiel van de Panne, Eugene Fiume, Zvonko G. Vranesic
Reusable motion synthesis using state-space controllers. SIGGRAPH (1990)
Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
A Detailed Router for Field-Programmable Gate Arrays. ICCAD (1990)
Lap-kong Chan, Zvonko G. Vranesic
TORMLAN - A Multichannel Local Area Network Protocol. INFOCOM (1990)
Mostafa I. H. Abd-El-Barr, Zvonko G. Vranesic
Cost Reduction in the CCD Realization of MVMT Function. IEEE Trans. Computers 39 (5) (1990)
Jonathan Rose, W. Martin Snelgrove, Zvonko G. Vranesic
Parallel standard cell placement algorithms with quality equivalent to simulated annealing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (3) (1988)
Wayne M. Loucks, William I. Kwak, Zvonko G. Vranesic
Implementation of a Dynamic Address Assignment Protocol in a Local Area Network. Comput. Networks 11 (1986)
Mostafa I. H. Abd-El-Barr, Safwat G. Zaky, Zvonko G. Vranesic
Synthesis of Multivalued Multithreshold Functions for CCD Implementation. IEEE Trans. Computers 35 (2) (1986)
Jonathan Rose, Wayne M. Loucks, Zvonko G. Vranesic
FERMTOR: A Tunable Multiprocessor Architecture. IEEE Micro 5 (4) (1985)
Kuang-Wei Chiang, Zvonko G. Vranesic
Comments on "Fault Diagnosis of MOS Combinational Networks". IEEE Trans. Computers 33 (10) (1984)
Paul Chow, Zvonko G. Vranesic, Jui Lin Yen
A Pipelined Distributed Arithmetic PFFT Processor. IEEE Trans. Computers 32 (12) (1983)
Kuang-Wei Chiang, Zvonko G. Vranesic
A Tree Representation of Combinational Networks. IEEE Trans. Computers 32 (3) (1983)
Kuang-Wei Chiang, Zvonko G. Vranesic
On fault detection in CMOS logic networks. DAC (1983)
C. L. Lam, Zvonko G. Vranesic
Key compression using segment strings. Inf. Syst. 6 (2) (1981)
Zvonko G. Vranesic, V. Carl Hamacher, Wayne M. Loucks, Safwat G. Zaky
TORNET: A local area network. SIGCOMM (1981)
Zvonko G. Vranesic, Kenneth J. Thurber, Sperry Univac
Teaching Computer Structures. Computer 13 (6) (1980)
Hussein T. Mouftah, Kenneth C. Smith, Zvonko G. Vranesic
Ternary Rate-Multipliers. IEEE Trans. Computers 29 (10) (1980)
Zvonko G. Vranesic
Review of Content addressable parallel processors by Caxton C. Foster. Van Nostrand Reinhold Co. 1976. SIGARCH Comput. Archit. News 7 (1) (1978)
A. Druzeta, Zvonko G. Vranesic
A. Higher Radix Technique for Fault Detection in Many-Valued Multithreshold Networks. IEEE Trans. Computers 27 (11) (1978)
Zvonko G. Vranesic
Multiple-Valued Logic: An Introduction and Overview. IEEE Trans. Computers 26 (12) (1977)
F. M. Valenti, Zvonko G. Vranesic
Experiences with CHUTE. ACM Annual Conference (1977)
Donald A. Sheppard, Zvonko G. Vranesic
Fault Detection of Binary Sequential Machines Using R-Valued Test Machines. IEEE Trans. Computers 23 (4) (1974)
A. Druzeta, Zvonko G. Vranesic, A. S. Sedra
Application of Multithreshold Elements in the Realization of Many-Valued Logic Networks. IEEE Trans. Computers 23 (11) (1974)
Zvonko G. Vranesic, Kenneth C. Smith
Engineering aspects of multi-valued logic systems. Computer 7 (9) (1974)
Zvonko G. Vranesic, V. Carl Hamacher, Y. Y. Leung
Design of a Fully Variable - Length Structured Minicomputer. ISCA (1973)
Zvonko G. Vranesic, V. Carl Hamacher
Ternary logic in parallel multipliers. Comput. J. 15 (3) (1972)
Zvonko G. Vranesic, K. M. Waliuzzaman
Functional Transformation in Simplification of Multivalued Switching Functions. IEEE Trans. Computers 21 (1) (1972)
Zvonko G. Vranesic, E. Stewart Lee, Kenneth C. Smith
A Many-Valued Algebra for Switching Systems. IEEE Trans. Computers 19 (10) (1970)
K. M. Waliuzzaman, Zvonko G. Vranesic
On Decomposition of Multi-Valued Switching Functions. Comput. J. 13 (4) (1970)