Minimizing FPGA Interconnect Delays.

Stephen Dean Brown Muhammad M. Khellah Zvonko G. Vranesic

Published in: IEEE Des. Test Comput. (1996)

Keyphrases

high speed
hardware implementation
field programmable gate array
real time
real time image processing
artificial intelligence
low power
social networks
low cost
data acquisition
fpga implementation
systolic array
round trip
evolutionary algorithm
single chip