Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits.

Tomasz S. Czajkowski Stephen Dean Brown

Published in: DAC (2007)

Keyphrases

power reduction
high speed
power consumption
positive and negative
edge information
edge detection
hardware design
real time image processing
signal processing
significantly reduced
power saving
real time
data sets
analog circuits
quantum computing
chip design