Guy G. F. Lemieux

Publication Activity (10 Years)

Years Active: 2008-2023
Publications (10 Years): 13

Top Topics

Tightly Coupled

Instruction Set

Content Addressable

Heterogeneous Systems

Top Venues

Publications

Zhonghua Zhou, Yuxuan Pan, Guy G. F. Lemieux, André Ivanov
MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing. ACM Trans. Design Autom. Electr. Syst. 28 (5) (2023)
May Young, Alan J. Hu, Guy G. F. Lemieux
Cache Abstraction for Data Race Detection in Heterogeneous Systems with Non-coherent Accelerators. ACM Trans. Embed. Comput. Syst. 22 (1) (2023)
May Young, Alan J. Hu, Guy G. F. Lemieux
Cache abstraction for data race detection in heterogeneous systems with non-coherent accelerators. LCTES (2021)
Hossein Omidian, Guy G. F. Lemieux
Low-Level Loop Analysis and Pipelining of Applications Mapped to Xilinx FPGAs. FPL (2019)
Hossein Omidian, Guy G. F. Lemieux
Software-based Dynamic Overlays Require Fast, Fine-grained Partial Reconfiguration. HEART (2019)
Guy G. F. Lemieux, Joe Edwards, Joel Vandergriendt, Aaron Severance, Ryan De Iaco, Abdullah Raouf, Hussein Osman, Tom Watzka, Satwant Singh
TinBiNN: Tiny Binarized Neural Network Overlay in about 5, 000 4-LUTs and 5mW. CoRR (2019)
Hossein Omidian, Nick Ivanov, Guy G. F. Lemieux
An Accelerated OpenVX Overlay for Pure Software Programmers. FPT (2018)
Ameer M. S. Abdelhadi, Guy G. F. Lemieux, Lesley Shannon
Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories. FPL (2018)
Hossein Omidian, Guy G. F. Lemieux
Exploring automated space/time tradeoffs for OpenVX compute graphs. FPT (2017)
Joe Edwards, Guy G. F. Lemieux
Real-time object detection in software with custom vector instructions and algorithm changes. ASAP (2017)
Ameer M. S. Abdelhadi, Guy G. F. Lemieux
A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs. FCCM (2016)
Hossein Omidian, Guy G. F. Lemieux
Automated Space/Time Scaling of Streaming Task Graph. CoRR (2016)
Ameer M. S. Abdelhadi, Guy G. F. Lemieux
Modular Switched Multiported SRAM-Based Memories. ACM Trans. Reconfigurable Technol. Syst. 9 (3) (2016)
Michael Xi Yue, Dirk Koch, Guy G. F. Lemieux
Rapid Overlay Builder for Xilinx FPGAs. FCCM (2015)
Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip Brisk
Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (12) (2015)
Aaron Severance, Joe Edwards, Guy G. F. Lemieux
Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors. FPGA (2015)
Ameer M. S. Abdelhadi, Guy G. F. Lemieux
Modular SRAM-Based Binary Content-Addressable Memories. FCCM (2015)
Ameer Abdelhadi, Guy G. F. Lemieux
Modular multi-ported SRAM-based memories. FPGA (2014)
Ameer M. S. Abdelhadi, Guy G. F. Lemieux
Deep and narrow binary content-addressable memories using FPGA-based BRAMs. FPT (2014)
Alexander Brant, Ameer Abdelhadi, Douglas H. H. Sim, Shao Lin Tang, Michael Xi Yue, Guy G. F. Lemieux
Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using Razor. FCCM (2013)
Dirk Koch, Christian Beckhoff, Guy G. F. Lemieux
An efficient FPGA overlay for portable custom instruction set extensions. FPL (2013)
Aaron Severance, Guy G. F. Lemieux
Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor. CODES+ISSS (2013)
Aaron Severance, Guy G. F. Lemieux
TputCache: High-frequency, multi-way cache for high-throughput FPGA applications. FPL (2013)
Alexander Brant, Ameer Abdelhadi, Aaron Severance, Guy G. F. Lemieux
Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew. FPT (2012)
Zhiduo Liu, Aaron Severance, Satnam Singh, Guy G. F. Lemieux
Accelerator compiler for the VENICE vector processor. FPGA (2012)
Alexander Brant, Guy G. F. Lemieux
ZUMA: An Open FPGA Overlay Architecture. FCCM (2012)
Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA (2012)
Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip Brisk
Routing algorithms for FPGAS with sparse intra-cluster routing crossbars. FPL (2012)
Chris C. Wang, Guy G. F. Lemieux
Parallel FPGA placement based on individual LUT placement (abstract only). FPGA (2012)
David Grant, Graeme Smecher, Guy G. F. Lemieux, Rosemary Francis
Rapid Synthesis and Simulation of Computational Circuits in an MPPA. J. Signal Process. Syst. 67 (1) (2012)
Ameer Abdelhadi, Guy G. F. Lemieux
Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations. ReConFig (2011)
Jeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton
Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition. ReConFig (2011)
Xiao Dong, Guy G. F. Lemieux
PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess. FPT (2009)
Johnny Tsung Lin Ho, Guy G. F. Lemieux
PERG: A scalable FPGA-based pattern-matching engine with consolidated Bloomier filters. FPT (2008)