Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew.
Alexander BrantAmeer AbdelhadiAaron SeveranceGuy G. F. LemieuxPublished in: FPT (2012)
Keyphrases
- clock frequency
- parallel architecture
- high speed
- power consumption
- duty cycle
- feature selection
- low latency
- clock gating
- response time
- ensemble methods
- ensemble learning
- base classifiers
- weak learners
- block size
- mental states
- real time
- combining multiple
- primal dual
- parallel processing
- load balancing
- high frequency
- multi class
- video sequences
- learning algorithm