Hadi Parandeh-Afshar

Publication Activity (10 Years)

Years Active: 2006-2018
Publications (10 Years): 3

Top Topics

Control Algorithm

Top Venues

Publications

Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi
Exploration of approximate multipliers design space using carry propagation free compressors. ASP-DAC (2018)
Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk
Approximate quaternary addition with the fast carry chains of FPGAs. DATE (2018)
Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi
CAL: Exploring cost, accuracy, and latency in approximate and speculative adder design. DFT (2017)
Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne
Revisiting and-inverter cones. FPGA (2014)
Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). FPGA (2013)
Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
Shadow And-Inverter Cones. FPL (2013)
Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA (2012)
Hadi Parandeh-Afshar, Hind Benbihi, David Novo, Paolo Ienne
Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones. FPGA (2012)
Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne
Reducing the pressure on routing resources of FPGAs with generic logic chains. FPGA (2011)
Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk, Paolo Ienne
Compressor tree synthesis on commercial high-performance FPGAs. ACM Trans. Reconfigurable Technol. Syst. 4 (4) (2011)
Hadi Parandeh-Afshar, Paolo Ienne
Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs. FPL (2011)
Amit Verma, Ajay K. Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. FPL (2010)
Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Paolo Ienne
Improving FPGA Performance for Carry-Save Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 18 (4) (2010)
Hadi Parandeh-Afshar, Paolo Ienne
Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance. FCCM (2010)
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. ACM Trans. Reconfigurable Technol. Syst. 2 (3) (2009)
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
Exploiting fast carry-chains of FPGAs for designing compressor trees. FPL (2009)
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2 (2) (2009)
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj
3D configuration caching for 2D FPGAs. FPGA (2009)
Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne
A flexible DSP block to enhance FPGA arithmetic performance. FPT (2009)
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne
Using 3D integration technology to realize multi-context FPGAs. FPL (2009)
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
A novel FPGA logic block for improved arithmetic performance. FPGA (2008)
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
Efficient synthesis of compressor trees on FPGAs. ASP-DAC (2008)
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA (2008)
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. DATE (2008)
Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Parandeh-Afshar
Enhancing FPGA Performance for Arithmetic Circuits. DAC (2007)
Hadi Parandeh-Afshar, Mohsen Saneei, Ali Afzali-Kusha, Massoud Pedram
Fast INC-XOR codec for low-power address buses. IET Comput. Digit. Tech. 1 (5) (2007)
Hadi Parandeh-Afshar, Ali Afzali-Kusha, Ali Khaki-Firooz
A very high performance address BUS encoder. ISCAS (2006)
Hadi Parandeh-Afshar, Mohsen Ahmadvand, Saeed Safari
A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor. ICECS (2006)